Then you should also see this:Quote:
Originally Posted by xdan
http://forum.beyond3d.com/showpost.p...postcount=6391
Quote:
That gives a spreader size of ~45.7mm * 35mm and a die size of 364mm˛. Seems like Charlie was right after all.
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Then you should also see this:Quote:
Originally Posted by xdan
http://forum.beyond3d.com/showpost.p...postcount=6391
Quote:
That gives a spreader size of ~45.7mm * 35mm and a die size of 364mm˛. Seems like Charlie was right after all.
taking into account Poisson distribution gf104 has higher yields than cypress. i worked out the math, gf104 has 9% higher yields not considering parametric yield or redundancy.
And why does Nvidia only sell GF104 with disabled parts?Quote:
Originally Posted by Chumbucket843
So no, GF104 yields aren't as good as Cypress.
you have made a lot of assumptions so no, you dont know that.Quote:
Originally Posted by Piotrsama
I think nvidia is trying to get rid of gtx470 stock before introducing a full fledged gf104. Also gf104 has less transistors per mm2, that could aid in yields in comparison with cypress, despite the higher size. On the other hand amd has been producing cypresses for a year now so....Quote:
Originally Posted by Piotrsama
What are your initial numbers? You must have had something to feed into the equation.Quote:
Originally Posted by Chumbucket843
The only assumption I see here is your idea that you can compare yields of two very differently built chips using such a simple formula.Quote:
Originally Posted by Chumbucket843
You just have to see what they did with GF100.
Yields sucked, so they released a cutted down version to improve yields.
Same story with GF104.
Well ... where is the confirmation ? I don't see any measurement on these pictures :shrug:Quote:
NH - Early information has claimed a surface area of 366mm^2 with GF104, which is confirmed by these pictures.
Top of the page:Quote:
Originally Posted by Olivon
http://www.xtremesystems.org/forums/...2&postcount=26
http://mental-asylum.de/files2/gf104measure2.jpg
I have seen this picture informal but that's not a part of NH's newz :shrug:
You're right it's not a part of the NH news article but it is the truth nevertheless.Whether they just guessed it or they in fact used the wrong image(?) in the article is debatable.
What if the measurement of PCIE connector is wrong and it is 83mm, oops than may be the die size is 334...? :down:Quote:
Then you should also see this:
http://forum.beyond3d.com/showpost.p...postcount=6391
Quote:
The PCIe connector seems to be ~85mm in size , only seems to be ???: http://www.interfacebus.com/PCIe_16x_Connector.gif Thean may all you measure only seems to be...and it's otherwise.
That gives a spreader size of ~45.7mm * 35mm and a die size of 364mm˛. Seems like Charlie was right after all.
And from where and how are these numbers calculated....A guy just dropp this 45.7.....blah...? :down:
In two weeks i'll have my GTX 460 and i'll measure the heatspreader. :up:
http://mental-asylum.de/files2/gf104measure2.jpg
And i don't know with that angles but and limitation but the die is deeper inside.
http://image163.poco.cn/mypoco/mypho...1193928021.png
die area, transistors/mm^2, and defect density(units in defects/cm^2). defect density is manufacturing process dependent so it's the same for both. it is a top secret number but it can be estimated based on it's trend.Quote:
Originally Posted by cegras
http://www.icknowledge.com/trends/defects.pdf
here is some background info on yield models. i used the poisson model with more terms for higher accuracy.
http://www.siliconfareast.com/test-yield-models.htm
you need to look harder. i clearly said in my post that i disregarded parametric yield and redundancy techniques. these i dont know and i could only give you a guess. really my point is that having a larger die does not necessarily mean lower yields.Quote:
Originally Posted by Piotrsama
If that's the most up to date data you have available, I would find it extremely precarious to extrapolate defect density trends considering the smallest size they've got is 250 nm. Furthermore, as we see with the GF100, just because it's fabricated on a smaller node it doesn't mean it takes advantage of the defect density. Or maybe it does, since it's such a large chip ... who knows.
Fail...Quote:
Originally Posted by xdan
The PCIE connector is an industry standard.
Just think about what you said for a second.
They were counting the pixels, taking into account the angle, figuring out the ratios and using industry standard components, aka pcie connector, to figure out the die size.
These B3D guys have been doing it for years.
http://www.pcper.com/comments.php?nid=8452
that comes out to ~.015 defects/cm^2. it should be even lower now.Quote:
Although TSMC recently said the defect density of its 40nm technology has already dropped from 0.3-0.4 per square inch to 0.1-0.3, the sources pointed out that the improvement in overall yield still needs more time before catching up with market demand.
Seriously who let you in here?Quote:
Originally Posted by xdan
Quote:
Originally Posted by xdan
why dont you measure a pci-e connector on your card and put those numbers up ... they are all the same anyway
I didn't said these not so convincing words...
, judge that guy.....:rolleyes:Quote:
The PCIe connector seems to be ~85mm in size
I mean when you're sure about something and you can guarantee that thing you say "is" not "seems to be"'
So cut it off :mad:
And look better at the picture, it's about the cut angle in the PCIE conector....the measurement is after the angle cut.
http://mental-asylum.de/files2/gf104measure2.jpg
http://translate.google.ca/translate...&sl=auto&tl=en
NO way! The card lives!
wonder how much temps r lowered heheQuote:
Originally Posted by Boogerlad
Because it is ~85mm, he hand measured it. Not like he has special equipment to measure to the exact length.Quote:
Originally Posted by xdan
Yes, the measurement is after the angle cut, because he is showing that it is a straight line across, not at an angle...
Comeon.