The K10 stepping fiasco

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Originally Posted by LOE

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Originally Posted by shintai

Today..a 3Ghz Opteron can compete with a 3Ghz Woodcrest.

On the desktop a 3Ghz X2 can compete with a 2.4Ghz Conroe.

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with the 2Ghz K10 buggy part performing like a woodcrest at 2.33 Ghz, and keeping in mind K10 scales better both in terms of frequency and core count I would say your server speculation .. kind of... sucks...

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As much as I hate to agree with Shintai :p: , I interpreted his original statement as referring to today's K8 i.e. currently in server K8 Opterons are already clock-to-clock equivalent to Core-based Xeons but in desktop they trail.

In the server space I think Barcelona will cause significant acid-indigestion for Intel. Already, their superior platform means even with K8 overall power consumption and performance is competitive and with K10 they can hit the 1S 4C market they're been locked out of for 1 year as well as take the allout performance crown in 2S or 4S.

As for the desktop, outside of the ultra-enthusiast market I'm pretty sure Phenom's performance will be "close enough" to land ever-increasing OEM business. It's basically a race against the clock to switch to the K10 line top to bottom before they run out of cash

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Originally Posted by LOE

with the 2Ghz K10 buggy part performing like a woodcrest at 2.33 Ghz, and keeping in mind K10 scales better both in terms of frequency and core count I would say your server speculation .. kind of... sucks...

For the desktop it looks like K10 has a good chance of equaling the IPC of c2, it depends on how much improvement will a low latency high bandwidth memory subsystem result in. But I don't think 5% are out of reach, K10 is 4 data hungry cores. That plus the "at least 5%" from fixing bugs should bring K10 very close to penryn IPC wise. Penryn will still clock higher but the gap will be nowhere near the one that is between c2 and K8.

K10 has very good chances of wiping the floor with intel in server, and be competitive on the desktop front, it all depends on how will amd execute their manufacturing, so shintai you can spare yourself the fanboi stuff :) ... you know what, I actually don't think you're an intel fanboy, you just want amd to fail badly. I bet you will get nightmares and eventually lost your sleep, and your mind if amd fight back the performance crown :yepp:

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A 2Ghz K10 dont perform like a 2.33Ghz Clovertown.

The 5% is another bogus story. And I will gladly admit im wrong if not. But the already Core 2 killer with 2Ghz beating 3Ghz Core 2s and such is dead.

Talking about fanboy, how would you categorize yourself? I give a rats rear end about both AMD and Intel. But there is a reality we have to deal with.

Phenom will be 5% lower than current 65nm Core 2. For 45nm Core 2 its gonna be worse with 10-15% slower.

But again, we can just wait and see. And I can yet again for the nTh time tell the hypeboys: I told you so.

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Originally Posted by Shintai

A 2Ghz K10 dont perform like a 2.33Ghz Clovertown.

The 5% is another bogus story. And I will gladly admit im wrong if not. But the already Core 2 killer with 2Ghz beating 3Ghz Core 2s and such is dead.

Talking about fanboy, how would you categorize yourself? I give a rats rear end about both AMD and Intel. But there is a reality we have to deal with.

Phenom will be 5% lower than current 65nm Core 2. For 45nm Core 2 its gonna be worse with 10-15% slower.

But again, we can just wait and see. And I can yet again for the nTh time tell the hypeboys: I told you so.

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All wrong,but you get a 10 for super speculation on you part :p:

ok, just to cut the crap in this mess.

here's the steppings list:

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A0/A1 - not relevant

B0 - early DVT. these were simply to qual the platform, not much more. obviously that's also done at the A1 level, but, this was less of such. Some early benchmarks made use of this.

B1 - late DVT, sent to partners for final config and platform testing. Also the steppings used for the catastrophe that was AMD marketing. Contains several errata, most notably 281 which was a northbridge error that impacted Stream, FPU, Int performance. Required a BIOS workaround.

BA - production release stepping. resolved errata 281 in silicon and is shipping for profit in Q3. Partner release only (essentially) as it will be superceded by B2 stepping in Q4.

B2 - production release for high speed SE and 95w parts for Q4. Will be announced in November with revenue shipping and availability either at the end of Q4 or beginning of Q1. will supercede ALL part codes that utilize BA stepping. fixes more noted errata.

B3 - as yet unannounced stepping release probably coinciding with Shanghai release (if on schedule next year). if it is the Shanghai refresh, will contain min. 6mb L3 and mask improvements along with further RAS refinements. supposedly partners are receiving early silicon of this as well, but i'd state it'd probably be early fab. spins for compat. purposes.

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hope that clears things up and puts this whole issue to bed.

dave

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Originally Posted by informal

All wrong,but you get a 10 for super speculation on you part :p:

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Kinda funny that comes from you. Perhaps you should check your K10 posts before the launch. Kinda abit of a grand canyon scale between your predictions and the result.

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Originally Posted by Shintai

Kinda funny that comes from you. Perhaps you should check your K10 posts before the launch. Kinda abit of a grand canyon scale between your predictions and the result.

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kinda a funny way of saying it. i should use that elsewhere. :)

dave

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Originally Posted by dave_graham

ok, just to cut the crap in this mess.

here's the steppings list:


A0/A1 - not relevant

B0 - early DVT. these were simply to qual the platform, not much more. obviously that's also done at the A1 level, but, this was less of such. Some early benchmarks made use of this.

B1 - late DVT, sent to partners for final config and platform testing. Also the steppings used for the catastrophe that was AMD marketing. Contains several errata, most notably 281 which was a northbridge error that impacted Stream, FPU, Int performance. Required a BIOS workaround.

BA - production release stepping. resolved errata 281 in silicon and is shipping for profit in Q3. Partner release only (essentially) as it will be superceded by B2 stepping in Q4.

B2 - production release for high speed SE and 95w parts for Q4. Will be announced in November with revenue shipping and availability either at the end of Q4 or beginning of Q1. will supercede ALL part codes that utilize BA stepping. fixes more noted errata.

B3 - as yet unannounced stepping release probably coinciding with Shanghai release (if on schedule next year). if it is the Shanghai refresh, will contain min. 6mb L3 and mask improvements along with further RAS refinements. supposedly partners are receiving early silicon of this as well, but i'd state it'd probably be early fab. spins for compat. purposes.

hope that clears things up and puts this whole issue to bed.

dave

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Does this mean the performance difference between the fixed and unfixed arrata 281 can be seen in the anandtech benchmarks Dave?

Not at dave: let's not use this thread to have "no you are a fanboy!" conversations, we're all a fanboy, get over it.

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Originally Posted by Jakko

Does this mean the performance difference between the fixed and unfixed arrata 281 can be seen in the anandtech benchmarks Dave?

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again, the mark of any good "benchmark" is repeatability. s7e9h3n and I are currently trying to either replicate or provide other benchmarks on B1 cpus (i'll have BAs within a week or two) to be able to compare contrast them in the coming weeks.

basically, trying to undo some of the terrible work that's been put out there without a lot of understand. :)

if Anand and TR actually go back and re-test, i contend that there WILL be a difference in performance between the B1 and BA steppings. Whether that's 5 or 15%, really isn't the issue.

cheers,

dave

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Originally Posted by Jakko

Does this mean the performance difference between the fixed and unfixed arrata 281 can be seen in the anandtech benchmarks Dave?

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http://www.dailytech.com/Stumbling+i...rticle8804.htm

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But why stop at BA or B1. The 2.5 GHz samples featured on AnandTech's second article are of the newest roadmapped spin; revision B2. When Shimpi made the inference that the 2.5 GHz Opterons would be the closest thing to Phenom, he was hardly exaggerating. AMD's current roadmaps peg the the B2 stepping launch for Opteron and Phenom as mid-Q4 2007.

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rofl, so wasn't BA ready on the 10th? (then what a nice "hardlaunch") thats pathetic... so did AMD really send out BUGGED AND CRIPPLED chips to anandtech for testing? wow what GREAT marketing. wasn't BA ready or are they just plain stupid?

techreport tested a 2.5ghz chip and it wasn't much better anway..

dave do you REALLY believe shanghai is launching so early that it may succeed the b2 stepping? (which would put it in Q1/Q2'08)
or is the b3 stepping rather something like Intel's g0 which will be replaced 3-6 months later by shanghai (that'd be logical)

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Originally Posted by Jacky

rofl, so wasn't BA ready on the 10th? (then what a nice "hardlaunch") thats pathetic... so did AMD really send out BUGGED AND CRIPPLED chips to anandtech for testing? wow what GREAT marketing. wasn't BA ready or are they just plain stupid?

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since i've replied to this ad naseum elsewhere, Anandtech, in the grand scheme of things, is meaningless. the chips weren't crippled. errata is part of ANY cpu launch and, just to play fair, intel does the exact same thing. just because Anand "prosumer" Shimpi didn't receive BAs doesn't mean they're not shipping. Sun confirmed that they've already been receiving them yesterday when I talked to them. *shrug* cut and dry to me.

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Originally Posted by Jacky

techreport tested a 2.5ghz chip and it wasn't much better anway..

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*yawn*

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Originally Posted by Jacky

dave do you REALLY believe shanghai is launching so early that it may succeed the b2 stepping? (which would put it in Q1/Q2'08)
or is the b3 stepping rather something like Intel's g0 which will be replaced 3-6 months later by shanghai (that'd be logical)

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where did i say that?

i said:

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B2 - production release for high speed SE and 95w parts for Q4. Will be announced in November with revenue shipping and availability either at the end of Q4 or beginning of Q1. will supercede ALL part codes that utilize BA stepping. fixes more noted errata.

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where does that say that Shanghai is launching early?

even further:

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B3 - as yet unannounced stepping release probably coinciding with Shanghai release (if on schedule next year). if it is the Shanghai refresh, will contain min. 6mb L3 and mask improvements along with further RAS refinements. supposedly partners are receiving early silicon of this as well, but i'd state it'd probably be early fab. spins for compat. purposes.

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notice the words in bold.... "probably" "if on schedule next year" so on. again, i'm not saying that it will be, but, the F2 to F3 steppings on the 2000 series only took 1 year.

i also stated that "if it is the Shanghai refresh"....that means, it may not be.
shanghai isn't another new "core" as it were. It's still slated to be an L3 add and will, if history is any indicator, contain masking updates, more cache, more RAS features, etc. 'Dozer, et al. are the new cores.

hope that helps.

dave

So Dave, can it be safely assumed that the 2.5ghz chips received by Anandtech and Tech-Report were NOT B2 stepping, as B2 stepping has yet to be released?

This is whats bugging me, as Kubicki claims the 2.5ghz part tested by Anandtech was B2.

the parts they received, in accordance to what i've stated above, are EARLY B2 samples. notice the different stamping on the IHS and the handwritten text. they should have most of the errata eradicated (i don't know what was on that spin list) but should not be viewed as a production ready processor. However, given AMD's stated intentions of shipping these for revenue in Q4, i'm going to assume that by the end of this month/mid october, they should be in production form.

cheers,

dave

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Originally Posted by dave_graham

ok, just to cut the crap in this mess.

here's the steppings list:


hope that clears things up and puts this whole issue to bed.

dave

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Dave, can you elaborate on what Errata 281 ... it does not appear in AMD's errata list...

Also, not to poke fun but what is the difference between and EARLY B2 and a LATE B2 :) ...

Jack

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Originally Posted by JumpingJack

Dave, can you elaborate on what Errata 281 is... it does not appear in AMD's errata list...

Jack

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errata 281 concerns STREAM, FPU, and Int issues with the northbridge. I will try to get a more technical statement for ya.

cheers,

dave

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Originally Posted by dave_graham

errata 281 concerns STREAM, FPU, and Int issues with the northbridge. I will try to get a more technical statement for ya.

cheers,

dave

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Thanks.... appreciated.

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Originally Posted by MR_SmartAss

The errata fix wouldn't improve the performance. A new stepping(Cx) with a circuit redesign would be required to boost the performance.
Having the 2M L3 between the RAM and the L2 cache, a 5% performance improvement in average would be quite impressive.
IMO 10% IPC improvement with 50% faster RAM is impossible(I consider specFP_rate, Sandra memory bandwidth and such as useless benchmarks that doesn't represent processor performance ).
For real-world, lets take the s939 as example. It has twice the bandwidth of s754, but it is up to 5% faster. Even s939 with 1MB L2 and CL2 vs s754 512kB CL3 doesn't improve the performance for 10% in average.

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as i've stated, let's see when we get there. trying to secure all the hardware is a nightmare, so...it's going to take a bit. :)

dave

http://www.fudzilla.com/index.php?op...=3049&Itemid=1

http://www.fudzilla.com/index.php?op...=3050&Itemid=1

would explain a lot....

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Originally Posted by MR_SmartAss

The errata fix wouldn't improve the performance. A new stepping(Cx) with a circuit redesign would be required to boost the performance.
Having the 2M L3 between the RAM and the L2 cache, a 5% performance improvement in average would be quite impressive.
IMO 10% IPC improvement with 50% faster RAM is impossible(I consider specFP_rate, Sandra memory bandwidth and such as useless benchmarks that doesn't represent processor performance ).
For real-world, lets take the s939 as example. It has twice the bandwidth of s754, but it is up to 5% faster. Even s939 with 1MB L2 and CL2 vs s754 512kB CL3 doesn't improve the performance for 10% in average.

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if you are talking single core, you are correct
S939 not a big boost over S754
if you talk about multicores,you are wrong.....

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Originally Posted by GoThr3k

http://www.fudzilla.com/index.php?op...=3049&Itemid=1

http://www.fudzilla.com/index.php?op...=3050&Itemid=1

would explain a lot....

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hu.. he just sucks up any rumors he reads and makes new out of them...

he has said noting new, all this above was allready mentioned in the different topics here.

Im still playing the wait and see game, but only till november. :p:

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Originally Posted by MR_SmartAss

1) There is no s754 multicore

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http://www.farfromneutral.com/exodus...7/03/o_rly.jpg

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Originally Posted by MR_SmartAss

2) I am talking about same clocked s754 vs s939

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well i know what your are talking about,my point was that for single cores,bandwidth doesnt matter much,however,when you are getting to dual and quad cores,you will need a lot more bandwidht to feed all the cores

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Originally Posted by lapdog

Better late than never. Much better late then defective.

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My thoughts exactly.....cough....cough

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Originally Posted by Jacky

I hope for them they didn't. Imo the BA stepping was released and sold...

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BA is productized B1 according to Charlie D. :))