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^Llano should fill the market of the 730$ notebooks
but for someone who can afford HALF of that, a bobcat chip is great since it should handle all the NEEDs even though it might not handle the few WANTs, like detailed gaming. keep in mind i said "people shopping for sub 500$" not that everyone should be shopping for sub 500$ laptops.
OK,after reading the latest AMD blogs and looking at the known rumored/disclosed data,I'm ready to state my performance expectations :) :
Server(16C):
Highest clocked part ~2.5Ghz with 3Ghz Turbo on all cores active while TDP is not reached;105W ACP/140W TDP. 50%-60% aggregate higher throughput performance than 2.5Ghz 12 core MagnyCours,which is an average of spec int and spec fp rate,STREAM etc.Spec fp rate should get a higher boost in performance,around 65% when compared to 2.5Ghz 12 core MagnyCours(this is just derived by looking at AMD's simulated gains from last analyst day which seemed 30% higher for fp Vs int rate) .
Standard edition part ~2.3Ghz with 2.8Ghz Turbo on all cores active while TDP is not reached;80W ACP/115W TDP. 50%-60% aggregate higher throughput performance than 2.3Ghz 12 core MagnyCours,which is an average of spec int and spec fp rate,STREAM etc.Spec fp rate should get a higher boost in performance,around 65% when compared to 2.3Ghz 12 core MagnyCours(this is just derived by looking at AMD's simulated gains from last analyst day which seemed 30% higher for fp Vs int rate) .
High Efficiency part ~2.1Ghz with 2.6Ghz Turbo;65W ACP/85W TDP.
Desktop(8C)
8C ~rumored branding~ FX series (3-3.5Ghz range). High(est) end part ~3.5Ghz with 4-4.2GHz Turbo on all cores;125W TDP rating (@ 4-4.2Ghz in Turbo mode,I'm now thinking in favor of Zambezi "Turboing" more than Interlagos' 500Mhz). 15%-20% higher IPC in single thread integer workloads,similar or a bit better(30-40%) should go for fp workloads.15% penalty due to shared front end in multithread workloads.Super low power in idle mode,on the level of SB and Llano cores.Single thread/up to 4 thread turbo @ 4.5Ghz with power gating 2 or 3 modules with power draw below the half the maximum TDP value.My estimated multithread performance with and without all core Turbo : ~4.2x1.15x1.33/1.15=1.7x or 70%T / 3.5x1.15x1.33/1.15=1.4x or 40% higher than Thuban @ 3.3Ghz .My estimated single thread/up to 4 thread performance with and without Turbo : ~4.5x1.15/3.7=1.4x or 40% faster than 3.7Ghz(Turbo) Thuban in single thread applications and 4.5x1.15=1.55x or 55% faster than 3.3Ghz Thuban in applications that scale to 4 threads(Thuban can't use Turbo on more than 3 cores).
6C Performance series(3.2-3.7Ghz range). Highest clock ~3.7Ghz with 4-4.2GHz Turbo on all cores;95W TDP rating.MT estimated performance : 12% w/o Turbo faster and 27% with Turbo faster than 3.3Ghz Thuban. Single thread/3 thread performance estimate : 40% faster than 3.3Ghz/3.7GhzTurbo Thuban.
4C Mainstream series(3.3-4Ghz). Highest clock ~4Ghz with 4-4.2GHz Turbo on all cores;65-95W TDP rating.MT estimated performance(apps scaling to 6 cores efficiently) : 25% slower w/o Turbo and 19% w/Turbo slower than 3.3Ghz Thuban. Single thread/2 thread performance estimate : 40% faster than 3.3Ghz/3.7GhzTurbo Thuban.
All is speculation on my part,but I'm pretty sure the numbers will be in the ballpark :).
edit: all above estimates are for integer workloads. SSE/fp workloads should get additional boost but I have no idea if Turbo will engage in the case of vectorized fp intensive multithreaded workload.If it doesn't engage then above numbers should be corrected(divided by 1.2x and multiplied by the difference in IPC between integer and fp,which is totally unknown :D).
Yes, that would stop SB sales. It would also stop current product sales.Quote:
Originally Posted by maxionline
Why would this be good for any company?
I have been in this business for 20 years. It is generally never good to release benchmarks prior to launch.
It seems JF-AMD confirms my point of view, but there is a difference that he is in the business opposite to you and me. That way please do some research next time and dont think that you know better, because apparently you dont.Quote:
Originally Posted by [XC] hipno650
But as you mentioned you're a ignorant, selfish person and that way I'll end my conversation with you right now.
Quote:
Originally Posted by [XC] hipno650
its obvious youll miss the point we are making .. thus you wont see the bigger picture ...
how do you think amd would recuperate on the money lost by the lack of sales of current product if they announce something way better with pricing and performance graphs etc...
they would officialy stick it to us ... yes us as in the customer .... now think for us ... yes us .. the customer .... and wait a bit more ... be patient
Intel dit it for years, no problem ... :shrug:Quote:
Originally Posted by JF-AMD
now take a look at the leftover intel stock on the marketQuote:
Originally Posted by Olivon
amd is going to clear their stock before BD launch ;)
But at the same time they weren't selling any CPU's to anyone who was in the know. I seem to remember everyone (including all my friends) saying that Pentium 4 was the best CPU and Intel was better. That's what you get with brilliant marketing and your hands down the OEM's trousers.Quote:
Originally Posted by Olivon
They don't tend to do it as much anymore and when they do it's usually because performance is orders of magnitude better than the previous gen, to them they've already sold all their CPU's anyway as they are sitting with the OEMs.
For example go into PC World/(whatever you call it in US/World) and count how many computers are there with Intel's in them, those are all SOLD from Intel.
That's what I believe anyway, not saying it's a good or bad thing...
INF: heh, nice,I hope for this :)
Can anyone tell me why we dont have the BD presentations from ISSCC yet ?? I cant find a single link
NDA maybe?:confused:Quote:
Originally Posted by Aten-Ra
Yea I'd love to get more info on BD (Zambezi especially). When would the info gathered on this meeting be revealed to public?
One way or another, I'm sure Dresdenboy will get hold of the information and give us some nice analysis :).
So the thesis to not release any performance numbers before the launch is that amd is going to lose the sales to big oems because when they know how much better the next chip is, they wont buy current ,right ?
But dont they know already ? I mean ES chips are already to some extent out there, or they will be shortly.So Dell/HP/Lenovo, they all know or pretty much will know shortly.
AMD is currently cornered into the value segment, and chips in this segment tend to sell even if much more capable solutions are available just becuase theyre somewhat cheaper.
And moreover this logic is double sided sword, there MAY be some lost sales due to some clients waiting,but on the other hand some clients will go Intel route because they offer much better chip and they dont have any info to think otherwise in the near future.
Only people that will be seriously affected by non disclosure of perf data are goin to be us, not even joe average.And JF said many times that we are to small to matter, so either way i dont see a problem :confused:
Big OEM's don't need public statements from AMD to have access to that kind of numbers. They do "background business" :D My guess is that they have X millions chips sold even before public launch :)
Rav, you must be patient ... no one is seriously affected other than people that can't have the patient to wait. They are not doing something out of extraordinary ...
Now, people that can't wait and are impatient will think 1000 things about AMD for not saying anything ;)
Also,CB has a die picture of a single module :
http://img638.imageshack.us/img638/864/98746539.jpg
Summary on CB.
edit :
More in PCWatch article translated.
Summary from article:
-custom flip-flop design is used to achieve high(er) operating frequency and keep power consumption at bay.USes more silicon area as a trade-off
-used 8T memory cells for higher clock potential with lower operating voltage (uses a bit more die space as a trade-off)
-design is specially optimized for clock and low(er) power,3.5+Ghz clocks are achievable and around 20% higher clock potential than previous design(family 10h on 45nm?)
Waiting for Cebit :)
Heh, for Cebit hope finally preview 900 AMD boards :). ANd some demo with Zambezi system of course :)
Looks like we can expect nice overclockability from the new AMD CPUs. :yepp:Quote:
Originally Posted by informal
It seems like it matches the lower modules in the earlier die shot that was floating around.Quote:
Originally Posted by informal
The upper ones seems more PS'ed, the lower ones are just blurred.
Don't get too fired up about CeBIT. That is being run by our EMEA team. The would not disclose anything that HQ has not already said.
As to the benchmarks and OEMs, stop for a moment and consider that OEMs and the retail channel (where 80%+ of client processors are sold) works on an inventory system with weeks of inventory built up and boxed in various stages of warehouses around the world. The last thing they want is anything that disrupts the flow of boxes out of the retail locations. And the fact that all of their SB systems were put on hld, they are already in a bit of pain from that, so a stall in AMD would make it doubly bad.
The problem with benchmarks is they make it REAL. Everyone knows BD is coming, it is not a secret. The guy who has to buy a new computer this week will buy one because he has to have one. But if he sees an official benchmark from AMD, he probably starts to think "hmmm, this is right around the corner, prices will come down on the old stuff when new stuff comes out, maybe I should wait a couple of weeks...." Play that out a few million times around the world and you see the impact it can have.
Anyone that is waiting for BD will wait. Nobody has come this far only to give up in the final stretch. And let's face it, SB might have been a big threat a month ago, but there are things that could have changed that equation....
Intel did not release an official benchmark on SB until launch. Yes, there were benchmarks floating around that may or may not have come from them, but they did not officially release anything because they have the same OEM problem.
Yeah they only "accidentally" leaked information when Conroe was on it's way to get rid of the kettle boiler sorry P4Quote:
Originally Posted by JF-AMD
Umm, no.Anandtech had a preview.Besides that, there was :banana::banana::banana::banana:load of leaks going around :up:.We pretty much knew what to expect few months before the launch.Quote:
Originally Posted by JF-AMD
Besides, with the information above you agree that DYI market is pretty big overall.
And the same logic works both ways, in example ,a user needs machine, so he can build something now with information he has already, and thats going to be intel for anything more than a cpu upgrade mostly :-/.2500k destroys any serious consideration of current x6 phenoms.And BD wont be a value chip for some time, so if he wants cheap he will go AMD one way or the other.Having information bout BD doesnt really change anything in the low margin level,and at the mid-high end it potentially disrupts intel sales.
Same goes for the chipset sales, you guys wait with AM3+ compatible solutions to clear the stock of older ones, but in exchange people buying now dont want to get stuck with unapgradable technology.
SB slip helped you alot in those regards i must admit tho.
yes and intel owns a larger portion of the total market .....Quote:
Originally Posted by Olivon
JF said "they did not officially release anything". Not leaks and whatnot. Now whether those leaks were deliberate or not is a completely different story...Quote:
Originally Posted by RaV666
My bad,intel released unofficially some previews/benchmarks.And then at IDF talked in depth about architecture, revealing clocks, architecture,models,sockets and some performance numbers :up:.All that 4 months prior to launch.(comparing lynnfield to sandybridge).Oh, and pricing ;-)Quote:
Originally Posted by eXceededgoku
based on SYSmark sure, I use that all the time to decide what will be my next build :rofl:Quote:
Originally Posted by accord99
EOL platfrom against new, lets see how the new SB when they arrive will be positioned.... Its actually a miracle that you didn't compare it to a Pentium :DQuote:
Originally Posted by Hornet331
Yea you're right I will wait and see how BD turns out but that doesn't mean I wouldn't still concider SB if BD doesn't perform well enough. Seeing how I'm an overclocker, BD will have tough competitor against 4.8~5GHz SB. :)Quote:
Originally Posted by JF-AMD
I expect AMD overclocks to improve too but somehow beyond 4.4 ~ 4.6GHz starts feeling like a stretch, hopefully I'm wrong though but it looks a bit worrying if the single-threaded performance won't improve more then the predicted by some people here 15~20% or so.
You think 8C BD @ 4.8-5GHz(OCed) will have a tough time against SB at the same speed? Probably yes in superpi.Almost certainly not in multithreaded applications ;).Quote:
Originally Posted by RPGWiZaRD
Thuban,which was not a high frequency design, with 6 cores on 45nm does 4Ghz on air today :). Imagine a 32nm grounds-up 8 core design with highK/mg,with specialized circuitry that allows higher frequency and lower power draw(for a bit larger die area),that was designed for higher working frequencies. It will certainly OC very well.The only question an enthusiast may ask is : Is there a cold bug ? :D
informal: really think, its possible 5 GHz at AMD with Zambezi? Im not pesimistic, but I thought about 4.5-4.6GHz stable...If will be 5 GHz at air/watter, Il suprised! But about performance know, Zambezi will be great in multithreading :)
Orochi is specially designed to hit higher clocks on 32nm. With manual OC you will probably see a higher OC than Thuban on air(which sits at around 4Ghz).20% above 4Ghz is around 4.8Ghz. But I'm just going along what is known so far,who knows how the actual chips will behave in reality.
Well multithreaded performance isn't so far a big deal to me seeing how at least in 90% cases it runs near its full potential with 4 cores for the tasks I do, in fact I'm not even interested in the 8C BD but 6C, at least until software developers have an efficient/easy way of using all cores efficiently. In 1 -1½ years there will be a lot better 8C chips out there for a more fair price too (8C will ofc have slight premium today). But let's just wait and see, maybe BD will suprise us positively with OCing seeing how Sandy often gets limited by multiplier before the frequency wall is hit (talking aircooling, ofc it's very obvious with LN2 or any of that kind of cooling) and BD shouldn't have such "issue" so you can push it harder instead (on Intel that won't help currently).Quote:
Originally Posted by informal
when looking at just turbo speeds, many people are hitting 4.3ghz on air with thuban, so i would imagine that one can clock higher with less cores if the limit is heat management. thats why i will probably go with a 4C unlocked BD chip, its rare i ever use more than that (unless the price for 6 is too good to pass up)
BUT at the same time you will have 4 strong cores if you go with the 8C BD, where each one will have access to more L2 and more bandwidth from the scheduler (look at me trying to act like i know something, lol. sorry if my exact details are a little wrong).
an 8C chip with very good settings/speeds for turbo should be 5-10% stronger than 4 threads on a 6C or 4C BD based on all having the same clocks.
Im pretty sure 15% number is the "worst case" scenario thing, taking into consideration new SSE SSSE AVX instructions alone in specific tasks/codes it should perform a lot better.Its not like sandybridge is ALWAYS 50% faster than phenom II too.Im hoping at least.Quote:
Originally Posted by RPGWiZaRD
you make an assumption as the line of work im in..... or not in.....;)Quote:
Originally Posted by Shadov
the computer industry is not just my hobby it's my job. I have personal experience in most levels of the retail (and OEM) market and I can tell you that doing a preview (like Intel did with SB) will make a microscopic impact on what happens to the current sales numbers. it will make a small difference in the enthusiast community but thats small change compared to OEM volumes. like i said before the vast majority of consumers (average Joe to international business) buy product when they need it. they will not wait around for the newest and UNTESTED platform to come out. in fact in many cases businesses will opt for an older platform because it is familiar and known to be stable. look what happened with the SB launch it would have paid off to get last gen stuff rather then SB because of the chipset problem.
I will say it again for the 18th millionth time. both AMD and Intel have absolutely no problem moving old stock even after a new chip comes out.... best buy as a company moves more more AMD CPU's in your city everyday then all of the custom shops put together. thats not including every other large scale store around.... not to mention the corporate sector. I still see Dell workstations ship with Core 2 Duo CPU's for retarded amounts of money.
you also missed the point where I said that I UNDERSTOOD why AMD keeps a lid on things. I just think it's for different reasons then you keep bringing up. but you also failed to give a good reason why you care if AMD takes a business risk or not. another thing for anyone to realize is that these larger corporations (AMD, Intel, Nvidia etc) are not concerned about us on a small scale... why should we be so concerned about whats good for them marketing wise why they could care less about us? thats like saying I hope AMD does not release the a competitive video card so that Nvidia can continue to charge me an arm and a leg for the fastest video card on the market so they can make more money and have a secure future..... as a tech enthusiast and consumer of tech parts I would rather have as much knowledge about new products and cheaper prices rather then know AMD or anyone else will have a "more secure future"
I will say it one last time.... don't attack me personally, there is no need. if you disagree thats fine for you and if you would like to explain why Im all for that because no one of us knows everything... but attacking me does not make your point any better...
In Multithreaded applications like Cinebench, h264, Pov-Ray and more, the 4 core 8 threads SB has no chance against a 4 module 8 core BD. I would say (my estimation) that SB will need ~1GHz OC to catch the 4 module BD.
In single thread, i would say a nice average 15-20% increase in IPC will not be too stretched for BD.
And here comes the big battle, 6-Core 12 threads SB-E vs 4 module 8 threads BD. I expecting the two of them to trade blows with SB-E to have better IPC and be faster in single threads but BD to give a nice fight in the Multithread domain.
Again, the one to have a better price/performance will win ;)
Why leak now when you can leak later?
AMD probably will leak/announce when Sandy Bridge motherboards come back to market. Most people will be a stone's throw away from a system purchase then.
yea and you an later compare that to the quad core 160 shader 28nm fusion coming out in 2011 which should keep your ultra monster SB busy.Quote:
Originally Posted by duploxxx
UPDATE: Bulldozer module shot(compared with Westmere)
http://i54.tinypic.com/vxgmiw.jpg
I know such situations very well (incl. the red colored one :D). Oh, and of course I agree with your points.Quote:
Originally Posted by Shadov
so little! Whau!
More info:
http://www.pcper.com/article.php?aid=1083
Nothing especially new, more of a summary I guess.
UPDATE 2: Bulldozer Module VS Magny-Cours
http://www.computerbase.de/bildstrecke/33300/2/
http://pics.computerbase.de/3/3/3/0/0/4.jpg
8-core SBs are coming to desktops though.Quote:
Originally Posted by Aten-Ra
and how many market share in % intel has ????Quote:
Originally Posted by RaV666
;) think about it ... intel can be intel .. and amd needs to do what they do .....
And how much are we looking at ?? Lets just hope BD overclocks extremely well otherwise its gonna be a useless hexacore chip which only runs well "with multi threaded programs" as people say..Quote:
Originally Posted by informal
multithreads is not bad idea, because is more and more multithreading aplications/games....If will working in ussualy singl soft 15s or 30s, doesnt matter. If will encoding video 5000s or 2000s, here is my time precious :).
It appears that it's been pulled.Quote:
Originally Posted by undone
Found another source:
http://www.abload.de/img/47mob.jpg
One extra integer pipeline, then?
Looks like a damn smart and efficient design, tbh, hope it works out well...
Agreed, it's the best of both worlds when it comes to multithreading and IPC.Quote:
Originally Posted by zalbard
If you're a guy who doesn't need more than 4 cores, the cores get the FPU and cache to themselves and thus more single threaded performance.*
If you're a guy who likes threaded applications, you get to leverage the threaded power of the architecture for more threaded performance.
*I'm curious to know if the Bulldozer design tries to prioritize single threaded apps to their own modules, does anyone know if this is the case?
It could be more efficient to use one module if that means it can turbo (higher) instead of two when using a lower amount of threads. At least from a power consumption perspective it could be smarter to use one module instead of two.Quote:
Originally Posted by JkS
2 threads in a module at 90% IPC of seperate modules at 110% speed will be ~100% performance but power consumption should be lower.
Good points marten_larsson. There are still a few things we don't know about the design,so I guess we should wait and see how the cores are handling the workloads when workload is less threaded(than the core count).
I would expect that responsibility ultimately ends up at the OS thread scheduler's mercy (or use of direct thread binding). It should still pose a similar situation as Hyper-Threading/SMT, the scheduler could use whatever logical processors it wants, however it *might* not necessarily know how to optimize for the underlying micro-architectural implications, e.g. the logical to physical mapping and their resource-sharing relation.Quote:
Originally Posted by JkS
The more I hear about Bulldozer, the more I see it as an adaptation of the ideas inherent in the UltraSPARC T2/3 architecture, with AMD mainly emphasizing single-thread latency instead of going all out on throughput :p:
i think i understand what you meanQuote:
Originally Posted by marten_larsson
example:
4 threads each on their own module might use 70% of the TDP and overclock 10-15%
vs
4 threads on 2 modules which would use about 50% of the TDP and overclock 20-25%, but have 5-10% less IPC due to shared resources.
in the end it might actually break even or be negligible differences for either route, which is kinda good since it means no matter how messed up windows is at deciding threads, BD knows how to overclock for max performance.
Manicdan there is also a cooperative prefetch bonus when threads share same L2 cache,which in turn may increase the performance to some degree.But maybe it's already counted in the already mentioned 80% boost when module is fully loaded. The shared frontend will act similarly to intel's SMT in other beneficiary way:it will smooth out inefficient usage by filling unused integer pipelines as quickly as possible ,just as SMT functionality does on one intel Nehalem/SB core.Only in AMD's case we have a whole core to grab the data,not just a vacant port in the execution stack ;).That's why AMD can see 80% increase from 2 threads and intel sees 20%-25%.
If im not mistaken, DENEBs integer Execution unit has 3 integer pipes PLUS 3 Loas/Store (AGUs) pipes when Bulldozer Integer Execution Unit has 2 integer pipes PLUS 2 AGen(Address Generator).Quote:
Originally Posted by zalbard
So we have 3 int pipes for DENEB vs 2 int pipes for each BD Integer Execution Unit.
it's 3 ALU/AGU for K10, they are general pipes. ( the third pipes give 5% more performance said by AMD ).Quote:
Originally Posted by Aten-Ra
it's 2 specialised ALU, and 2 specialised AGU. so it's more faster on integer on Bulldozer. And i think this is a more efficient disign about power comsuption.
That's early! Epic! :eek:Quote:
Originally Posted by andos
Edit: wait, it's not a release, it's a presentation. Or do I get it wrong?
ok lets all hold hands and pray for just one benchmark
How credible would we consider cebit here?Quote:
Originally Posted by andos
That's an official statement.Quote:
Originally Posted by FlawleZ
That's the official Cebit page... Pretty credible if you ask me. But unveiling does not equate launching.
if it is 50% then... it has to be BD? perhaps they will name them phenom III?Quote:
Originally Posted by informal
http://www.abload.de/img/47mob.jpg
Well, first the above slide is a little bit misleading for someone that dont knows the DENEB (Magny Cours) architecture.Quote:
Originally Posted by madcho
Secondly i believe the slide wants to show the difference of the CMP vs Bulldozers Cluster-Based Multithreading design and so the slide is not an accurate representation of Denebs (Magny Cours) Integer/fp Execution Units.
Denebs integer execution unit has 6x pipelines, 3x ALUs (Integer) and 3x AGUs (Load/Store) and the Integer Scheduler can issue 6x MicroOP (uops) to it.
Bulldozer integer execution unit has 4x pipelines, 2x ALUs (Integer) and 2x AGen(Address Generators) Plus a Load/Store unit (40 Load/24 Store) and the Integer Scheduler can issue 4 uops to it.
The DENEB don’t have FP FMACs but 3x Pipelines, FADD, FMUL,FMISC
Bulldozer FP has 4x pipelines, 2x 128-bit FMACs and 2x 128-bit MMX and one FP shared Scheduler that can issue 4x uops to the FP execution unit.
lol isnt the MC pic supposed to be of bobcat?
No more Phenom, no more Athlon. Probably it will be simply called AMD FX.Quote:
Originally Posted by god_43
i think your mixing up one major thingQuote:
Originally Posted by Aten-Ra
deneb has 3x pipelines, but they can do EITHER, NOT BOTH at the same time.
so 2 alu and 1 alg
or 3 alg and 0 alu
but not 3 and 3 at the same time
BD is always going to do 2 alg and 2 alu per core
First of don't like the design nor do I trust the bold assumption/statement made for bulldozer here (perhaps, just have to see myself as currently still consider AMD making same mistake than Intel). Also, I think HT calculation is a bit inaccurate considering ratio is closer to 165% not 118% (and not by being intel fanboy just been testing a lot of their cores), but even this 165% sucks as it's never stable for general application code for real cores. I wonder what would similar application pressure do to AMD bulldozer like server database pressure against high clock would it uberly fail like Intel's HT or still calculate correctly.
What ever happened to 'real cores' only strategy.
"Real cores" still exist. Instead of using up die space for real cores, AMD has managed to almost achieve the performance of two real cores by using shared resources. Think about it. You can achieve 85 to 90% performance of two real cores with 1 module but you're reducing logic die space, heat and power consumption. All good IMHO. :clap:Quote:
Originally Posted by genetix
I do understand this. I just prefer solid real cores only no matter would the "virtualized" cores do clean 200% that only means so could the actual module/core. Makes big decesion when we talk about real cores if it comes up to 4 modules or clean 8 core XEON you can be pretty sure it ain't gonna be modules :)Quote:
Originally Posted by freeloader
but that's an bad example I am just saying I dislike the idea how current architectures are build.
Just a reminder -- the CPU does not schedule, the OS does. Questions about how threads are distributed should be investigated at the OS level. I.e. How much has AMD worked with MS to understand the most effective, efficient scheduling?Quote:
Originally Posted by informal
I think JF once said they are collaborating with MS on how BD thread scheduling will be handled per AMD's own suggestions(since they should know best as day designed the thing :) ).
Yep. Wouldn't surprise me. Regardless if it is SMT or CMT, there is an asymmetric distribution of resources between two shared vs two physically different cores (or modules to retain the same level of meaning).Quote:
Originally Posted by informal
Best performance would to distribute over module first then pair up. I am certain this is being comprehended within the OS for BD.
Yes my bad, Deneb has 3 pipesQuote:
Originally Posted by Manicdan
I've heard something about Vision A4, A6 and A8.Quote:
Originally Posted by Oliverda
Seems logical and like a traditional AMD move. A4 sounds better than i3 and so on.
About the cebit bit, didnt JF told us to dont expect anything about BD at cebit ? Maybe its about Liano, current amd solutions (zacate withstanding) are kind of sub par so maybe that how theyve come with the 50% bit:shrug:
But JF also said that he don't know anything about what's going on at the desktop side.Quote:
Originally Posted by RaV666
From where im standing he said to us that there isnt going to be any new information on CEBIT about bulldozer.Theres no way to intepret this sentence differently :shrug:Quote:
Originally Posted by JF-AMD
It would be great tho, to atleast see the machines working.
Any comparison vs. MC would come from my blog. Period.Quote:
Originally Posted by undone
old architecture is 3 ALU/AGU pipelines which are shared. New architecture is 2 ALU + 2 AGU, all dedicated.Quote:
Originally Posted by Aten-Ra
Don't expect much, this is not a luanch.Quote:
Originally Posted by zalbard
yes, that was a typo, we corrected it since thenQuote:
Originally Posted by Aten-Ra
yes, but launch plans are shared between divisions, and I was having a beer with the desktop BD guy last monday, we stay in contact.Quote:
Originally Posted by -Boris-
IMHO there is a higher chance for FX.Quote:
Originally Posted by -Boris-
4 cores BD - AMD FX-3xxx
6 cores BD - AMD FX-5xxx
8 cores BD - AMD FX-7xxx
for example...
Fixed ;)Quote:
Originally Posted by Oliverda
numerically 4,6,8 sounds faster than 3,5,7 without even knowing anything other than the part number.
But the whole FX-XXXX is a bad idea. People will learn that FX is a processor but they won't learn which one to get. Where I work, when people talk about processors they just say i3, i5 or i7. People really don't care which i5 it is as long it's an i5. Cause they know that an i5 is good enough. Calling all bulldozers for just FX will make people confused.Quote:
Originally Posted by Oliverda
How is using FX# any different than i#?Quote:
Originally Posted by -Boris-
Higher the # the better.
Its the same as iX ,its pretty much identical :-).Quote:
Originally Posted by -Boris-
i-X
FX-X
Besides, most i5`s are only dual core, which kinda makes your coworkers kinda moronic.
i3 vs FXQuote:
Originally Posted by thematrixhazune
i5 vs FX
i7 vs FX
See the difference?
The four digit numbers is nothing people care about. As I said, when people talk about intel CPUs the usually just say i5 or i7. Customers understand that i7 is the best one and so on. If you start talking about FX 4650 vs. FX 6450 people will be confused. People care about series, like i5, Core 2, Phenom II, Sempron. Not about modelnumbers like 940BE or E6400.
A4 and A8 is simple.
Not with four digits after the FX prefix. And my coworkers mostly sell computers to small companies and schools. i5 is good enough in most cases.Quote:
Originally Posted by RaV666
accualy, the phenom and athlon brands will be gone. all that will remain will be vision. vision black, professional, and ultimate. dunno what is what, what will go above what. this is just a rumour
+1 with Boris
most people are not intuitive enough to realizing that the first number for the 4 number string have a pattern about the basic performance of the chip. unless someone is familiar with the entire LINE they will not be able to know whats high and low, end up getting pissed off cause they feel stupid, and never care to learn how the numbers work.
i would rather see FX8-xxx, FX4-xxx
and based on what weve seen sofar with E and C numbers, maybe AMD is sticking with 3 numbers after the character label.
Intel has more numbers too, ItsQuote:
Originally Posted by -Boris-
->Intel Core i7 990X for example
So
->AMD FX8xxx
is different how ?
Besides, this debacle is kinda pointles we have no confirmed model designation, not even ONE :-)
So the possibility of:Quote:
Originally Posted by -Boris-
FX4-xx
FX6-xx
FX8-xx
is out of your world and can never exsist?
And again i5 is stupid as it both holds quad and dual cores, and i dont think amd will be any better tho. We've already seen the naming of the first fuzion parts brazos, wich are: C30/50 and E-240/350 in wich both series contains single and dual cores wich is just stupid. The E-series should have both been dual cores and C single core.
Honestly I think BD is targeted against i7, lliano will take on against i5&i3.Quote:
Originally Posted by -Boris-
that would be true if AMD only called it FX. but they will have # afterwards to show the difference. Say for example we were talking CPUs and you told me the new i8 will spank the new FX 8000's. You wouldn't need to state FX 8123Quote:
Originally Posted by -Boris-
unless I am missing something on the naming..
First off, english isn't my native language and im pretty drunk at the moment. Please have some understanding for my unusually bad english.
But people outside the enthusiast community just say i7 or i5, the numbers afterwards are to complex or to confusing. So it would be i7 vs. FX. People won't care enough to realize the difference between FX 4800 and FX 6400. People don't memorize 4 digit numbers. The last three numbers will take the focus away from the first one enough to make people not memorize the series.Quote:
Originally Posted by RaV666
As I said earlier. People remember series, like i7, i5n A8 and A6. Not modelnumbers like FX 6450.
That wasn't one of the alternatives that I was arguing against.Quote:
Originally Posted by Kristers Bensin
It looks like there will be 2, 3 and 4 module Bulldozers, maybe even one single module.Quote:
Originally Posted by Mechanical Man
People will miss the first digit in the 8123 number. People won't remember if the 8 is part of a more complex number. Do you think ordinary people would remember ior even realize the difference between intels series if they were named Core i 5560 or Core i 7990X. Core i5 and Core i7 is much simpler and easier to remember.Quote:
Originally Posted by thematrixhazune
I once again apologize for any spelling errors. English isn't my native language, it's late friday evening and Im drunk. :shrug:
thats a pretty sad statement = / , Whats wrong with dual cores ?Quote:
Originally Posted by RaV666
Quote:
Originally Posted by -Boris-
+1, agree with you. Most of the people only talks about i3 or i5 etc
they won't care if i5 dual core or quad core part. Until they bought it, discuss with IT savvy friends and found out...lolz
Even most mobile i7s are dual core.Quote:
Originally Posted by RaV666
I remember when Intel introduced it, it was confusing, but now it seems everyone is use to it.
I am sure the same thing will happen with AMDs FX / A / E line, the nice outcome for AMD is that you can (hopefully) easily tell if its a 2/3/4/6/8 core, whereas for Intel you sometimes have to look it up on some spec table.
HMm no ...Quote:
Originally Posted by JF-AMD
If you mean "shared" in the sense like Bulldozer's Decoder is shared between two INT clusters, then your statement ist wrong.
These pipelines are there since the good old AMD K7 days, they consist of a pair: one AGU for adress generation and one ALU for any other, normal INT calculations.
Nothing is shared between those two pipeline. Some may count the scheduler, but that one is shared even to a higher degree in Bulldozer, too.
However, sharing in that context is a good thing, the unified scheduler is more flexible in assigning ALU and AGU Ops to the ALU/AGU pipelines. Nevertheless the theoretical, maximum throughput of Bulldozer is only 2AGU+2ALU ops per clock, whereas a K10 could issue 3+3 in the best case.
Because of the better efficiency, Bulldozer might still have the higher throughput in reality, but the 3 against 4 pipeline picture is still wrong from a technically point of view.
See also here:
http://www.chip-architect.org/news/O...teger_Core.jpg
http://chip-architect.com/news/2003_...it_Core.html#1
(ALUs 0,1,2 and AGUs 0,1,2 are clearly visible, they are not one big shared entity)
*sorry i was wrong*