please tell me how bad my reading comprehension is ...
because all i read was bla bla bla bla i know better then some big corporation .... ;)
ohh and btw *censored word* you too ;)
some little kid Freeolader dont stop flaming :-/. Just simply, AMD is not INtel and have different strategy - so, buy SB or waiting at Zambezi. Maybe some benchmarks will be leaked befire launch, but I am thinking, earlier in March or so...
http://1.bp.blogspot.com/_rWv20AgRpf...freeloader.jpg
A poll has been added
If they hide performance maybe we are gonna see some nice performance then...also the comeback of the FX series make me excited about next generation processor.
No sane company would do a preview so long before launch.
All it does is stall sales (since new & better is coming) and also it gives heads up to the competition on what they have to expect and how to structure prices.
So that way no, not going to happen until AMD and Intel have 50/50% market share, so previews will be similarly risky for each one of them. :shrug:
I remember amd giving performance previews before the phenom launch, turned out to be lies anyway so no biggy. If I remember it was not a full review or benches but they did a few slides with numbers. Why not do that now? They could time it with sb launch, just a few slides, come on:).
it looks like AMD employees vote for the first answer of the poll :)
I voted the first one as well, it makes sense from a business perspective.
I think AMD will release numbers when the time is right (either officially, or through controlled leaks).
Well, AMD have done preliminary tests for Zacate - letting even the press test some stuff. So much for the "no bechmerks before launch" policy. :p:
Otoh, you can't canibalize a non existent market and it was only two months till launch, so I guess it was a good move in that situation.
AMD started shipping Brazos on the day November analyst day was held(9th of Nov). Zacate numbers embargo was lifted on the 16th of Nov,a week after they officially announced they started to ship Brazos to their partners(an unofficial launch if you will). More facts next time :),but nice try :p: .
Does that mean I can buy Brazos stuff in stores already?? Wow, I must have been living under a rock for 1.5 months.... :)
Following that logic, can we expect performance numbers in February or whenever Bulldozer starts to ship or has it's "unofficial launch"?
If yes, then it's fine with me. :)
The difference is, AMD has no competing parts for that market segment from own camp, contrary to Zambezi which will compete with Intel solutions as well as AMD's own lower grade solutions for desktop market.
That's why AMD let Brazos platform to be reviewed ahead of market availability.
Can't speak for zacate, we don't share silicon on that one so it's not my call. As I understand, they did demos, I don't think they submitted benchmark results, but I don't really know what client benchmarks are these days so I really can't say.
Performance numbers too long before launch can would possibly have the following affects:
Numbers are great:
-Hurt Intel but not handicap
-Decimate current AMD sales
Numbers are good:
-May or may not hurt Intel
-Destroy current AMD sales
Numbers are bad:
-Sky rocket Intel's sales
-May or may not affect current AMD sales
Its pretty much a lose lose for AMD at this point IMO. ~5 months is too soon.
I don't agree with no preliminary reviews, makes you think something stinks about the new architecture. Moreover though I want AM3+ mobos available some time before BD so I can get my system prepared to just simply drop in a new CPU as and when.
Correction, All benchmarks are only approximations based on several assumptions.
To date, there is yet to be one valid benchmark on predicting user experience improvement.
A benchmark that is good at predicting performance at some tasks are often terrible at predicting performance for other tasks. [Numeric analysis often requires features and additions that are considerably expensive in terms of transistors. That would negatively effect all other scientific calculations.]
I did acknowledge that two posts above the one you quoted.
That's a solid logic I can't argue with. :)
But in the end, what effectively happened is, we got perf numbers before launch, since as far as I understand AMD still keeps their hand on the launch date, which is tomorrow, or so I heard. If it was up to the OEMs we'd surely see some products launch before Xmas and some reviews, right?
Makes me wonder why Intel let some benchamrks before launch be done and canibalize (or not?) it's own sales...
do you think will see bulldozer engineering samples at CES?
no, CES is all about bobcat, not bulldozer
Crazy how it's now officially 2011, Sandy Bridge is going to be released and BD hopefully in a few months. Wow. BD better come out swinging, because if Intel's 2500K & 2600K trade blows with the 980x, imagine what their higher-end 2011 processors will do. At this point it would be kind of stupid to buy 1156, 1366, AM3 processors if you are building a new system based around a $200-$300 CPU.
the problem is the lack of hype, or even performance information we are getting, as indicated BD is due to be released this year and yet we have very little to go by except the slides which were released months ago.
I can quantify a couple of hundred people I know have been waiting for any BD data, anything which can indicate real-time performance, and it looks like the lack of information will mean that they are going to go for intel products.
I understand that you're not the one in charge of withholding information, but at least I hope what your enthusiast and mainstream consumers will do because of it.
Is it that the bigger picture will benefit the company far more?
I've been with the company for close to 5 years and the whole time we have released benchmarks with launch. We typically do something like a STREAM benchmark before launch, but that is only a memory bandwidth benchmark. If you look back you will see that this has been the case for quite some time.
Sandybridge is supposed to launch this week, I have not seen an official intel benchmark, have we? This is how the industry operates. We all remember Osborne, at least those of us that are old enough do.
http://tof.canardpc.com/view/d051b5a...a3ffa053b2.jpg
Intel got margins to go to 95W TDP :yepp:
edit : Sorry, Hardware.fr's gif was on my cache and deep linkin' isn't supported
Starting production in March and Launching a month later? That means they'll have ZERO problems? And they'll be rushing themselves? I don't like it one bit.
I know that because I can read :shocked::shocked::shocked:
http://www.hardware.fr/articles/815-...dy-bridge.htmlQuote:
Intel s’est laissé beaucoup de marge avec un TDP à 95 watts sur ces processeurs, et leur consommation réelle est une bonne surprise par rapport à leurs spécifications. Du fait de l’Hyperthreading, le Core i7 consomme notablement plus en charge que les Core i5.
That's crazy, isn't it ? :D
If we were talking about a >six month difference then I'd understand (as in when we all thought the 800-series would work with BD), but if the difference is less than say three months, what's the gain? Unless you're missing a board right now.
It's better to wait for the CPU launch, and meanwhile trying to figure out which boards that are good, unless you feel like going guinea pig.;)
You know the 900-series won't be that spectacular anyway without a BD, so there's no need to be the first. .
Bulldozer Module is completely different.
HyperThreading only appears like two cores to the OS.
In reality it only uses the second thread to reduce the amount of time the core spends doing nothing whenever there's a stalled thread.
So for a core without hyperthreading:
cache miss occurs -> requests correct data from memory -> waits for it to arrive -> continues thread
A core with hyperThreading:
cache miss occurs -> requests correct data from memory -> instead of waiting for it and processing the first thread, it starts processesing the second thread.
Each Bulldozer module does actually have the hardware to process two threads simultaneously. It is actually two cores.
HyperThreading doesn't and can't make the one core process two threads simultaneously. It just reduces the time it spends waiting because of stalled threads.
Time*quantity/per core= performance
Even if Amd will have more cores, if they don't reduce also the time in wich a core do the operationS iT's ussless...
Of course they are increasing per-core performance. The only question is how much.
I think most likely IPC will at least reach i7 level if not SB level.
Then there's the question of frequency, which depends on manufacturing and materials.
With 32nm and HKMG we can expect better frequencies for sure - again, only question is how much.
And power efficiency depends on a combination of manufacturing, materials, design
Performance depends on a combination of IPC, frequency, and memory access (getting data to/from the cores fast enough for the cores to keep working).
looking at IPC alone only gives you a part of the picture, and looking at frequency alone only gives you part of the picture
That's why we have to see how it performs. They had a lot of time to develop brand new design.Old one had a few bottlenecks,especially in the execution stage of the pipeline. New core has more flexibility in EX stage and support many new features(wider fronted being able to effectively decode 4+1 x86 instructions(branch fusion),unified math and address scheduler in integer cores, 2x more load/store BW Vs 10h,much much better prefecthing,better branch prediction,4x larger L2 that is shared between core pairs,partitioned L3 that is now 8MBs large,complete ISA support,FMA support,universal FPU design which is able to execute even 2 FADDs or 2FMULs if needed etc.).
There is a LOT of things in BD and if they done it right it can be a lot faster than Thuban. With standard(average) IPC jump of 15%,pure core count jump of 33% and clock jump of 20% with much higher aiming Turbo core versus Thuban,this thing can go a lot higher. Interlagos has the same 33% higher core count and in throughput it's claimed it is 50% faster.Zambezi will have 2x less cores than Interlagos so this means higher clock rate are very possible(stock and Turbo),so 50% of Interlagos advantage may turn in same or somewhat higher number with Zambezi Vs Thuban.
It's like trying to put 10 pounds of data in a 5 pound bag. While HT allows a single core to handle 2 threads, it can only handle one at a time. There is only 1 set of integer pipelines, so while 2 threads are initiated, only one is active.
It is like the ability to date 2 people. Anyone can date 2 people, but the ability to do both at once is very rare, if not non-existent.
You have no idea what you talking about. Have you?
Your comparisions are really wrong and misleading.
Interleaved hyperthreading (only one thread at time can be actived on each core) is used only in itanium. All x86 hyperthreaded cores can really handle 2 threads at time (depending on available execution resources). But since in most cases there are available execution resources (a single thread rarely utilize even 70% of available core execution resources), so HT mostly shows positive effect. This is really simple and elegant way to utilize resources which are already in place but not used.
BTW i don`t know if I`m posting here correctly but, are there any rumours regarding the APU that will use a Zambezi CPU and a highend 28nm GPU?I think I saw some slides somewhere that it might launch this year.And one other thing, where did this rumour regarding BD`s IPC < SB came from? did AMD themselves actually said that it will be lower?
HOLD ON...
If the desktop version of BD, Zambezi will be here in April, the server parts should arrive a few months prior correct? Can we expect Interlagos in February?
Fortunately there is a Globalfoundries who is firmly working on a 28nm node as well.
Server parts will come later in this case. This time they won't wait after the Opterons launch to start the desktop parts. It's a smarter choice. :)
And since server parts are "the more cores the merrier" I think there's no point in releasing a "simple" 8-core Bulldozer but focusing instead on the 12-16cores MCM parts (Interlagos).
badboy18187
AFAIK
Trinity APU 32nm 2012
Bulldozer 1.5 (based on Komodo?)
Better IGP than Llano
Krishna/Wichita APU 28nm Q4 2011 by rumors
Improved Bobcat cores (probably based on Llano cores)
Better IGP (160SP Caicos HD6450 or low end Llano IGP?)
Zacate is 40nm, it's impossible to have one part of the chip at 40nm and another in 28nm. It's one or another, but not both.
Llano will be interesting though, it's at 32nm and have 6 times as many shaders as Zacate, and will have 4 enhanced Phenom II cores but without the L3.
And about that IPC rumor, much in BD has been streamlined for as low amount of trannies as possible, and sometimes they made a performance trade off to lower the die size and enhance performance per watt or performance per mm².
So it might be a very efficient processor per watt, or per mm², at the cost of IPC. But it might be so that the other will make up for this trade offs.
Anyway, these enhancements aloow 8 cores at a relatively small die, and they might allow a high frequency design which is relatively cool. Might mean 4GHz+ at introduction.
Llano now have 4MB of L2 or 1MB L2 cache/core if I'm correct.
Actually hyper-threading was criticized for being energy-inefficient. For example, ARM has stated SMT can use up to 46% more power than dual core designs. Furthermore, they claim SMT increases cache thrashing by 42%, whereas dual core results in a 37% decrease.
Not to mention that in May 2005 Colin Percival demonstrated that a malicious thread operating with limited privileges can monitor the execution of another thread through their influence on a shared data cache, allowing for the theft of cryptographic keys.
Hyperthreading is largely a strong negative effect to any system.
Adding performance feature will add some power consumption. This is natural. I can't comment ARM design, but SB is very efficient even with HT.
http://images.anandtech.com/graphs/graph4083/35052.png
Cache trashing is mostly function of cache size and quality of software. In fact Bulldoser will be affected in the same way as SB with HT since each module uses shared cache (while dedicated L1 was reduced to just 16k).Quote:
Furthermore, they claim SMT increases cache thrashing by 42%, whereas dual core results in a 37% decrease.
Well... This is funny. In fact, no absolutely secure hardware exists. There was introduced Blue Pill malware which uses security holes in AMD virtualization technology. Can we say AMD-V is a "strong negative effect" to any system?Quote:
Not to mention that in May 2005 Colin Percival demonstrated that a malicious thread operating with limited privileges can monitor the execution of another thread through their influence on a shared data cache, allowing for the theft of cryptographic keys.
Hyperthreading is largely a strong negative effect to any system.
Update:
Since you used wikipedia as your source of information, I just want to add a sentence which you forgot to copy:
In May 2005 Colin Percival demonstrated that a malicious thread operating with limited privileges can monitor the execution of another thread through their influence on a shared data cache, allowing for the theft of cryptographic keys.[15] Note that while the attack described in the paper was demonstrated on an Intel Pentium 4 processor with HTT, the same techniques could theoretically apply to any system where caches are shared between two or more non-mutually-trusted execution threads; see also side channel attack.
Also:
In 2010, ARM has stated that it will include simultaneous multithreading in its chips in the future.
:confused:
http://images.hardwarecanucks.com/im...ybridge/16.jpg
(source: hardwarecanucks.com)
The cache on intel gets trashed before the cache on phenom, L3 on i7 is 16-way set-associative and on Phenom it is 48-way set-associative.
I think that Bulldozer will have strong prefetchers that works on the L2 cache. The size indicates that they are using that trick to gain speed. Same trick that Intel have worked hard on and as I think, many applications is optimized for.
Only if you are using a weakly parallel or single threaded program, and only one instance/program at a time.
There are only a few real world high performance usage scenarios I can think of where that is the case (ie. gaming). For most high performance work people I know run multiple programs at the same time and those programs often have multiple intensive threads. There is a reason I have mostly had multi-processor or multi-core machines since the pentium pro days.
If it comes down to a case where SB is faster with low thread counts and BD is faster with high thread counts, then you can't go by such a simplistic statement as what you made. Nor can you simply go by most review sites either, they usually run a single benchmark at a time. You will have to look at the types of programs you use AND how you use them before you can determine what will have the best performance for your scenario.
Are most people going to put that much thought into their purchasing decisions? Lol, hell no.
quality of implementation is largely independent architectural superiority.
Similar arguments can be made about many poor designs being better than superior architectures.
cache thrashing generally refers to data cache [which Bulldozer keeps separate]
Also I wish to note that I am attempting to discuss hyper-threading independent of any implementation and am not discussing security faults in x86 in general,
See above
I think the shared L2 per core pair with a size of 2MB is going to be a big deal for many desktop apps.Redpriest over at SA forums once said that AMD suffered a lot because many apps were optimized for just that cache size as a sweet spot (on intel HW since past Core2 they had very fast and large shared L2 cache). AMD finally tackled this issue with fairly large and fast L2. Compared to Thuban,in single or poorly threaded desktop workloads there is now 4x more L2 cache running at full clock with 2x greater load/store BW than Thuban core. Further,the L3 is now 33% larger and partitioned with 2.4Ghz+ frequency(20+ percent improvement Vs Thuban).
Just looking at cache subsystem BD is on whole other level than Thuban.
It might look flawed,but in reality,whatever was optimized for Core2 ran at least equally well or better on Nehalem. Small but very fast private L2 and large but still fast shared L3 was a design decision that came from monolithic die approach for quad core Nehalem(and similar in Barcelona's case).
It certainly is IPC related, HT helps in most cases to improve the total number of instructions retired per clock by overprisioning the frontend and taking advantage of long latency siutaitons.
http://www.xtremesystems.org/forums/...&postcount=169
Guys, first photo of AM3+ board from MSI
http://pcper.com/images/news/ces2011/amd_am3+.JPG
BIG thanks for Daveburt :)
http://pcper.com/comments.php?nid=9584
Yeah, I mixed it up with mobile HD7xxx news. The top mobile card isn't coming out until Q1 2012.
Dude, I edited. See above.
Not sure I understand this statement... HT is one of many methods used to increase IPC. Saying it is IPC related but not HT related is a contradiction.
As the graph linked here shows HT usually improves performance, and in the worst case has no affect on performance. Presumably the benchmarks where performance does not improve are not heavily threaded ones.
About HT: How good is hyperthreading?
Hyperthreading does indeed give a measurable advantage that shows in benchmark tests. This is a strong sales argument that may convince the confused consumer. But the microprocessor designer should also take into account that few applications are able to handle hyperthreading optimally. This is a technology that places a considerable burden on software developers as well as on operating system designers. We may ask whether the silicon space that is used for implementing hyperthreading might be better used for other purposes?
i dont like HT simply because it confuses people when they hear 8 threads and check their task manager, and they think its just going to be twice as fast, instead of 0 to 40% faster.
so in the end i would call it a marketing gimick rather than a real solution to a problem of not enough cores.
Not sure my wife would like that strategy
When you have 70% of your pipeline filled, you have 30% available for the second thread. But in really efficient code, if you have 90% filled, 10% is available, and there are cases, like Linpack, where HT gives you negative performance increase because the overhead of managing cache and threads is greater than the benefit from performance.
Desktop in Q2
Server in Q2
That is all AMD has said.
That just means that their cycles lined up ahead of theirs. Who goes first is based on schedules.
People get caught up in believing that there is some consistent relationship between who launches first, but it is more tied to readiness and launch opportunities than to some pre-determined order.
I heard only, first will be now desktop and server later.
amd should and had better be rushing bulldozer desktop. sandy bridge overclocking to 4.7ghz makes everything else look retarded unless you are on the fringes. intel project selling a bajillion of them and with people coming out of a recession, if amd doesn't get the new sales, they might just miss the boat.
Take a look at this.
http://l31.sphotos.l3.fbcdn.net/hpho..._6953022_n.jpg
logo Phenom FX is strange...loks it as fake (logo)
PS: I hate fakers!
@ andos: source?
It's hosted from somebodies facebook account, that's all I know from the URL.
Can never tell what that 3.5ghz+ means.
http://www.semiaccurate.com/forums/s...8&postcount=72
Thanks, I try to liven up the forums every now and then, I also tried by modding that G1 killer board, but noone like it :(
Thanks J-F for all that, I think I will upgrade to dusty bridge for the first part of the year until 2nd gen BD is released, maybe late this year, who knows,