Originally Posted by
Ao1
EEC deals with correctable errors and as NAND geometry shrinks, instances of correctable errors increase exponentially. A correctable error does not necessarily mean the NAND cell is on its way out. Any improvements that may be available in the future have to be offset by the continuing growth of page sizes as geometries shrink. I really can’t see anything that is going to reduce WA below what it is already (without compression), especially if page file sizes continue to grow, but then again I’m not a NAND engineer.