Originally Posted by
Raja@ASUS
Looks like Intel shifted the POST calculation to include WCL from SNB onwards. Previously these two were tied on X58 and P55. IO-L is buffer latency and allows RTL to be shifted to account for any IO delays from the DRAM buffers (there is also a clock skew offset but that value is internal and calculated during POST).
EDIT: I should add that IO-L is an offset, the base value it is added to shifts so adjustment does not always help. The shifting in the base value is due to read/write levelling drift. This manifests at speeds higher than DDR3-2000 depending upon the DIMMs used (some DIMMs are okay to DDR3-2400). Basically you have to get lucky with training for stability.
The effective RTL time is likely close to: 8 X ((1000/Uncore Freq)+ Clock skew)+tCL. The IOL likely moves a pointer at the IMC FIFO buffer for data arrival on top of the RTL time. Uncore freq should be around DRAM Freq on this platform. I had a quick look at SNB last year and it seemed that is what Intel had done, I would assume it is the same here.
-Raja
