Guys,
Any help would be gratefully received?????
Quote:
Originally Posted by jspuds
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Guys,
Any help would be gratefully received?????
Quote:
Originally Posted by jspuds
Man, i'm havin a hellova time getttin my Q9450 stable @4.0... It seems that the bios "lacks" the fine tuning adjustments for runnin a quad anywere near the "4.0" mark..... I was thinkin of gettin a Giga P45, but i've got too much damn $$$ wraped up in all the Asus stuff i've got...... Your 9650 oughta be a bit easier with the 9x multi, but like i said, its the "fine tuning" thats gonna make it, or break it.....
here is my 9550 setup running @ 4.0GHzQuote:
Originally Posted by screwtech02
this is chip testing so thats why you see 1:1
http://i237.photobucket.com/albums/f...r/MII_4GHZ.jpg
here is the ram brought into play
http://i237.photobucket.com/albums/f...table_1130.jpg
Extreme Tweaker
Ai Overclock Tuner : Manual
OC From CPU Level Up : AUTO
CPU Ratio Control : Manual
- Ratio CMOS Setting : 8.5
FSB Frequency : 471
CPU Clock Skew : Normal
North Bridge Clock Skew : Normal
FSB Strap to North Bridge : 333
DRAM Frequency: DDR2-1131
Dram Clock Skew CH1 A1 : Normal
DRAM Clock Skew CH1 A2 : Normal
Dram Clock Skew CH1 B1 : Normal
Dram Clock Skew CH1 B2 : Normal
DRAM Timing Control: Manual
CAS# Latency : 5
RAS# to CAS# Delay : 5
RAS# Precharge : 5
RAS# ActivateTime : 18
RAS# to RAS# Delay : 5
Row Refresh Cycle Time : 65
Write Recovery Time : 6
Read to Precharge Time : 5
Read to Write Delay (S/D) : 10
Write to Read Delay (S) : 4
Write to Read Delay (D) : 5
Read to Read Delay (S) : 6
Read to Read Delay (D) : 6
Write to Write Delay (S) : 5
Write to Write Delay (D) : 6
Write to PRE Delay : 16
Read to PRE Delay : 6
PRE to PRE Delay : 1
ALL PRE to ACT Delay : 6
ALL PRE to REF Delay : 6
DRAM Static Read Control: Disabled
Dram Read Training : Disabled
MEM OC Charger : Enabled
Ai Clock Twister : Moderate
Transaction Booster : Manual
Common Performance Level [8]
Pull-In of CHA PH1 Disabled
Pull-In of CHA PH2 Disabled
Pull-In of CHA PH3 Disabled
Pull-In of CHA PH4 Disabled
Pull-In of CHA PH5 Disabled
Pull-In of CHB PH1 Disabled
Pull-In of CHB PH2 Disabled
Pull-In of CHB PH3 Disabled
Pull-In of CHB PH4 Disabled
Pull-In of CHB PH5 Disabled
PCIE Frequency : 101
CPU Voltage : 1.4375
CPU PLL Voltage : 1.57950
FSBT : 1.36500
DRAM Voltage : 2.19750
North Bridge Voltage : 1.43125
South Bridge Voltage 1.5 : 1.5
South Bridge Voltage 1.1 : 1.1
CPU GTL Reference 0 : Auto
CPU GTL Reference 1 : -45
CPU GTL Reference 2 : Auto
CPU GTL Reference 3 : -45
North Bridge GTL Reference : AUTO
DDR2 Channel A REF Voltage : AUTO
DDR2 Channel B REF Voltage : AUTO
North Bridge DDR Reference : AUTO
Load Line Calabration : Enabled
CPU Sread Spectrum : Disabled
PCIE Spread Spectrum : Disabled
Hope it helps
I'll give that a shot GRN, currently have my DKx48+ installed, what a Epic Fail this board is with a Quad, ugh.... You get that Rampage going yet???
I've been so busy lately and to top it all off my basement flooded when the road crew were working on the water mains.
Its supposed to rain all weekend so I really hope to have the Rampage running by Sunday
Not sure if this applies to everyone's boards, but mine seems to be very unstable between around 475 to 499 FSB. 470 FSB is fine, but it gets progressively less stable as it approaches 478 FSB, and is unstabilizable between 478 and 499 FSB. Sometimes at around 495 - 499 FSB, it won't even load windows.
For example, at 9 x 478 = 4302 MHz @ 1.28v it fails orthos in less than 2 mins, it doesn't make it to the 4th 8K test. However I'm currently testing 8.5 x 506 = 4301 MHz @ 1.28v all other settings the same (except the ram speed of course) and it has passed more than 2 sets of the 8K test and has been running error free for around 32 mins so far.
Perhaps it's worth testing if this applies to your board too, and although it may appear counter intuitive, going straight to 500 FSB from 470 - 499 FSB may help solve stability issues if you are experiencing them.
4301 Mhz (506 x 8.5) @ 1.27v - DDR2-1214 @ 1.96v - PL8
http://i720.photobucket.com/albums/w...14196v-PL8.jpg
Mine is quite stable between 470 and 490 FSB but I'm actually fighting with 500 (and I guess it will be the same at 495)...but it might also be due to the fact that I use higher mem frequency at that FSB. I will try to give more NB voltage to see if it makes a difference. If not, I will perhaps forget these values and try higher ones as I might be around the FSB hole.
Interesting, I didn't think it would apply to all boards though. Knowing my luck I got some POS M2F with a huge FSB hole, and it just so happens that the FSB hole is right where I want to run it 24/7. 500 FSB is where it's suddenly stable for me. I can run 500 x 8.5 on the 5:6 divider and it's fine, but I'd prefer to not have to run 1.96v through my good D9's 24/7 (ignore my sig it's incorrect).
Very strange behaviour indeed, interesting settings on that MB are around FSB hole so we are getting mad as it's not easy to determine if we are right inside or not. Another strange thing on my MIIF is that even unstable at 500 FSB I'm still booting at PL8, but at 515 I cannot even use PL9, only PL10...I have to investigate values such as 505/510 to see if I have chance to boot at PL9 or if it goes straight from PL8 to PL10.
Each board behaves differently. I can run PL8 up to 542 FSB stable, higher than that the board can't the frequency, 651 MHz is the absolute max, and that requires 150ps delay to keep it SPI32M stable. If I attempt to go higher, no amount of skew (or any other) adjustment will stabilize it. It's definitely not my ram, it is stable at 651 MHz @ 2.24v and I have had it higher totally stable on other boards.
You won the jackpot with your sticks, what are the reference? There is a shop in my area that is selling very cheap ones but I don't think they are the same: Xtreem Dark Series TXDD2048M1066HC5D.
I had a very short night and fortunately it's Friday so I will be able to sleep a lot tomorrow:). I started to test several FSB values from 490 to 510 and the board is perfectly stable until 496 with 1.39 VNB. After 496 FSB unstability occurs and sometimes it is stable and sometimes not, but as I didn't write on paper:confused: I will have to redo one or two of the tests to confirm. I think I could be stable using PL10 with 1:1 divider. BTW it's because of that divider that I couldn't boot the MIIF at PL8 passed 500 FSB. Changing the strap helped me to boot with no problem at PL8 (12:10 is probably the best for that board) but I will need RAM that can go up to 1300 to pass 500 FSB, mine are doing 1200 at 2.25 V and are d9gmh but I'm not confident with giving them more than 2.35 V.
One thing is certain, 497 FSB is my worse value and could be the beginning of a small FSB hole, nothing stable at that value while I can use a stable PL8 at 496. It could for be the same reason that many owners find it difficult to get stable around 500 FSB. I will do some more test to check if I can get stable at PL8/9 - 515/520 FSB.
The TeamGroup product code is TXDD2048M1066HC5DC (not the Dark series).
Your sticks should hopefully be able to do DDR2-1200 with less than 2.25v. Make sure you have Memory OC Charger enabled in BIOS.
Thanks mate. The OC Charger is already enabled and the maximum frequency I could reach with the 4 sticks together is 1200 at 2.2 V (they can perform a little more one by one). Now they need 2.25 V to get stable (about 80 errors in Memtest at 2.2V) and I don't know where it's coming from...as it's not a lot of volts it might be a change in the motherboard with months of use or just another fine tuning need...anyway I will not expect something spectacular like 1300 with these sticks.
I've been doing a little testing. This seems to be a pretty nice 24/7 setup, the main aim being to restrict the voltage as much as possible. This also has the obvious knock on effect of keeping things cooler too which is also good. I'm working on reducing the vNB now, as it seems the board was struggling at 470 - 499 FSB and now seems much more comfortable at 500 FSB. Setting NB GTL Ref to -40mv also added some stability at 500 FSB.
I realize vdimm reads as 1.98v in the SS, it was flicking between 1.97 - 1.98v under small FFT load, I happened to capture that while it was on 1.98v, but under HCI Memtest load, it sits solidly on 1.97v which represents approximate maximum memory stress.
4250 MHz (500 x 8.5) @ 1.256v / DDR2-1200 @ 1.97v / PL8
http://i720.photobucket.com/albums/w...00197v-PL8.jpg
Guys, can you share your 500x8 full bios config?
Sure:
Quote:
Ratio CMOS Setting: 8
FSB Frequency: 500
CPU Clock Skew: Auto
NB Clock Skew: Auto
FSB Strap to North Bridge: 333
DRAM Frequency: 1002Mhz
DRAM CLK Skew on Channel A1: Auto
DRAM CLK Skew on Channel A2: Auto
DRAM CLK Skew on Channel B1: Auto
DRAM CLK Skew on Channel B2: Auto
DRAM Timing Control: 5-5-5-12, others Auto
Auto DRAM Static Read Control: Deaktiviert
Auto DRAM Read Training: Aktiviert
Auto MEM. OC Charger: Deaktiviert
Auto Ai Clock Twister: Moderate
Ai Transaction Booster: Manual
Common Performance Level: 10
PCIE Frequency: 100
CPU Voltage: 1,218
CPU PLL Voltage: 1,50
FSB Termination Voltage: 1,179
DRAM Voltage: 1,80
North Bridge Voltage: 1,179
South Bridge 1.5 Voltage: Auto
South Bridge 1.1 Voltage: Auto
CPU GTL Reference (0): Auto
CPU GTL Reference (1): Auto
CPU GTL Reference (2): Auto
CPU GTL Reference (3): Auto
NB GTL Reference: Auto
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto
Load-Line Calibration: Deaktiviert
CPU Spread Spectrum: Deaktiviert
PCIE Spread Spectrum: Deaktiviert
eSp!s0
Thank you mate, but I need someone share 1200mhz ram mode with tight timings and subtimings
I'm not running 8 x 500 but I'm currently running 8.5 x 500, so it should be the same but with higher vcore. Remember your board & hardware will be a little different too, so this will just be a base to tweak from. I wouldn't call my ram timings 'tight' though, they are just average in my opinion.
Code:Ai Overclock Tuner: Manual
OC From CPU Level Up: Auto
Ratio CMOS Setting: 8.5
FSB Frequency: 500
CPU Clock Skew: Normal
NB Clock Skew: Normal
FSB Strap to North Bridge: 333MHz
DRAM Frequency: 1200 Mhz
DRAM CLK Skew on Channel A1: Normal
DRAM CLK Skew on Channel A2: Normal
DRAM CLK Skew on Channel B1: Normal
DRAM CLK Skew on Channel B2: Normal
DRAM Timing Control: Manual
1st Info: 5-5-5-15-3-30-6-3
2nd Info: 7-3-5-4-6-4-6
3rd Info: 14-5-1-5-5
DRAM Static Read Control: Enabled
DRAM Read Training: Enabled
MEM. OC Charger: Enabled
Ai Clock Twister: Moderate
Ai Transaction Booster : Manual
Common Performance Level [8]
Pull-In of CHA PH1 Disabled
Pull-In of CHA PH2 Disabled
Pull-In of CHA PH3 Disabled
Pull-In of CHA PH4 Disabled
Pull-In of CHA PH5 Disabled
Pull-In of CHB PH1 Disabled
Pull-In of CHB PH2 Disabled
Pull-In of CHB PH3 Disabled
Pull-In of CHB PH4 Disabled
Pull-In of CHB PH5 Disabled
PCIE Frequency : 100
CPU Voltage: 1.31875
CPU PLL Voltage:1.50000
FSB Termination Voltage:1.25900
DRAM Voltage: 1.98550
North Bridge Voltage: 1.28550
South Bridge 1.5 Voltage: 1.50000
South Bridge 1.1 Voltage: 1.10000
CPU GTL Reference (0): +60mv
CPU GTL Reference (1): +20mv
CPU GTL Reference (2): +60mv
CPU GTL Reference (3): +20mv
NB GTL Reference: -40mv
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto
CPU Configuration:
Ratio CMOS Setting: 8.5
C1E Support: Disabled
Max CPUID Value Limit: Disabled
Intel Virtualization Tech: Enabled
CPU TM Function: Enabled
Execute Disable Bit: Disabled
Load-Line Calibration: Disabled (I prefer droop it provides cleaner power to the CPU if you do not adjust vcore accordingly- target load voltage is 1.256v)
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
For anyone interested, here is my Orthos/Linpack/Memtest stable 4.3GHz (506 x 8.5) / DDR-1214 settings:
Code:Ai Overclock Tuner: Manual
OC From CPU Level Up: Auto
Ratio CMOS Setting: 8.5
FSB Frequency: 506
CPU Clock Skew: Normal
NB Clock Skew: Normal
FSB Strap to North Bridge: 333MHz
DRAM Frequency: 1216 Mhz
DRAM CLK Skew on Channel A1: Normal
DRAM CLK Skew on Channel A2: Normal
DRAM CLK Skew on Channel B1: Normal
DRAM CLK Skew on Channel B2: Normal
DRAM Timing Control: Manual
1st Info: 5-5-5-15-3-30-6-3
2nd Info: 8-3-5-4-6-4-6
3rd Info: 14-5-1-5-5
DRAM Static Read Control: Enabled
DRAM Read Training: Enabled
MEM. OC Charger: Enabled
Ai Clock Twister: Moderate
Ai Transaction Booster : Manual
Common Performance Level [8]
Pull-In of CHA PH1 Disabled
Pull-In of CHA PH2 Disabled
Pull-In of CHA PH3 Disabled
Pull-In of CHA PH4 Disabled
Pull-In of CHA PH5 Disabled
Pull-In of CHB PH1 Disabled
Pull-In of CHB PH2 Disabled
Pull-In of CHB PH3 Disabled
Pull-In of CHB PH4 Disabled
Pull-In of CHB PH5 Disabled
PCIE Frequency : 100
CPU Voltage: 1.34375
CPU PLL Voltage:1.50000
FSB Termination Voltage:1.25900
DRAM Voltage: 1.99175
North Bridge Voltage:1.29875
South Bridge 1.5 Voltage: 1.50000
South Bridge 1.1 Voltage: 1.10000
CPU GTL Reference (0): +60mv
CPU GTL Reference (1): +20mv
CPU GTL Reference (2): +60mv
CPU GTL Reference (3): +20mv
NB GTL Reference: -40mv
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto
CPU Configuration:
Ratio CMOS Setting: 8.5
C1E Support: Disabled
Max CPUID Value Limit: Disabled
Intel Virtualization Tech: Enabled
CPU TM Function: Enabled
Execute Disable Bit: Disabled
Load-Line Calibration: Disabled (I prefer droop it provides cleaner power to the CPU if you do not adjust vcore accordingly- target load voltage is 1.280v)
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
thank you, bro :up:
testing...
CryptiK
You have a little strange subtimings.
When I was on MF x38 i just set 5-5-5-15 and other subs on auto. Was stable.
When I moved on MIIF I can got error while running Prime after 2-3 hours.
In 2-3 days I will get the second CellShock kit. Until that I need fix my system.
And yes: on x38 i had 10600 Read. Now, i have only 10300.
What do you mean by strange subtimings? They are essentially auto, but three of them are pulled in a little tighter. Auto for my sticks comes up as:
1st Info: 5-5-5-15-3-42-6-3
2nd Info: 8-3-5-4-6-4-6
3rd Info: 15-5-1-5-5
Here's my CellShock 8000 C4 sticks at the settings I provided above.
600 MHz / 5-5-5-15 @ 1.97v / 500% dual HCI Memtest
http://i720.photobucket.com/albums/w...v-PL8vNB12.jpg
CryptiK
I have the same auto timings. Hmmm, I`m not stable with your setup...probably, your RAM is better
Trying more vDimm
Could be a few things. Set your vNB and NB GTL Ref to what you know is stable, then try the ram settings. Your ram may need a little more vdimm but it should be similar.
It seems i am stable using your setup but i had to increase vdimm to 2,05. Why my cellshock need more vdimm than your?
Not sure, I have 2 8000 C4 kits and they both perform the same. Probably just luck I'd say.