SLI on X58 or Skulltrail 2 and I'll be happy :)
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SLI on X58 or Skulltrail 2 and I'll be happy :)
I would expect Bloomfield boards to cost less than P45 boards... the X58 chipset is actually much simpler and should therefore cost much less than a P45 chip. It all depends on how Intel prices it of course.Quote:
Originally Posted by perkam
The components for the rest of the board will be pretty much the same except for the socket.
The only added complexity is the triple channel DDR3 which early reports indicated might require an 8-layer PCB however, I expect by launch the boards will be back to 6-layers. An added benefit of DDR3 is in-flight compensation for trace-length delay so the constraints on equalizing trace lengths for DDR3 are not as strict as they were for DDR2 giving board manufacturers more flexibility with regards to layout which should allow them to maintain 6-layer PCB's in spite of the dramatic increase in traces to route.
All of this won't stop ASUS from trying to soak early adopters however! :rolleyes:
Sure if there are 51, 52 and 55's. Users in this market made all the manufacturers confident in overcharging for the motherboards. X58 will be priced higher than X48 and yes I hope I'm wrong. Then there will also be something like a X55 that falls in-between the mid and high end products.Quote:
Originally Posted by virtualrain
My guess is we'll see $300-$375 for Bloomfield boards.
That is just what my gut tells me.
With regards to the concept of a virus that could be created specifically to make peoples multi/fsb/whatever change simply to annoy the user ... well ... I think any coder who knows enough to do that would get far more gain from doing what most virus writers do these days, spyware. :banana::banana::banana::banana:ing with people isn't really what viruses are about these days, its more about profit.
In other news, someone can (could?) already cause machines to reboot right now! Have you ever randomly chosen an IC in setfsb and told it to set an fsb or something? It isn't pretty.
t
Thanks very much JC,
I wonder if you have found any issue in the process.
Metroid.
Drwho? - how is the "Skulltrail 2" coming along? Can you tease us with some details? :)
Quote:
Originally Posted by Drwho?
Quote:
Originally Posted by Drwho?
Actually, you appear to have dodged the question posed with an alarmist diversion. Classic The_Ghost rebuttle 101...
(Too caustic?)
Thanks for sharing the benchs JC :up:
I saw no overclocking in the locked multi Bloomfields till now. Don't know if its due to early stage of motherboards or something else. Does anybody know anything about that?
How about temps, are they really hotter than Penryn at stock clocks?
I guess they locked the engineering samples to stop people from getting impressions from the very early versions. I think I read that somewhere.
Oh, and given that there are integrated memory controllers, QPI links and the like I think it would be strange for them to not be hotter!
That's why instead of Fines, the Sum-Bee-yotches should go to Jail and be shacked with Dewayne or Ricky Bobby types. Stealing more than $400 is a Felony, then it should be treated as such.Quote:
Originally Posted by taemun
Nehalem is going to Rock be it in single or multi threaded. I think too many folks are reading wayyyyyyyy too much into early boards and unoptimized software.
I might not do a Nehalem until next winter or so lol! Still can't wait to see what others do with their's.
Nehalem is designed electrically for 45nm Metal, penryn wasnt.Quote:
Originally Posted by bowman
how was penryn not designed for the high-k dielectric?Quote:
Originally Posted by Shintai
Based on tick-tock,
the process comes first and then a new architecture that is built on that process.
Penryn is just a die shrink of Conroe with a few enhancements. It was originally designed for 65nm. Nehalem is designed from the ground-up to be built on the 45nm process technology.Quote:
Originally Posted by Fuji
Even if they've enhanced it there's supposed to be gains from designing it ground up for the already tried and true process technology.
You've got it backwards. Penryn is a derivative of the Merom family. Merom was designed specifically for 65nm and Penryn is a "die shrink" with minor updates for the 45nm node. Nehalem is designed specifically for 45nm and Westmere is the derivative process shrink of Nehalem on 32nm. Similarly, Sandy Bridge is specifically designed for 32nm and so on and so forth.Quote:
Originally Posted by Fuji
and how much is power wat energy PC system for your Nehalem?
Exactly... and there are numerous reports that when Intel caught wind of AMD doing a native quad on 65nm, they simply admitted they couldn't do it. An interesting statement given the struggles that AMD has had but at the same time a bit of endorsement to AMD's engineering to have been able to pull it off.Quote:
Originally Posted by bowman
At any rate, I think both AMD and Intel will demonstrate that 45nm is "the" process at which a native quad becomes really viable.
It wasn't when they caught wind of it, it was several months after AMD unveiled the barcelona design. And Intel's statement was more along the lines that it would be foolish to attempt it rather than they couldn't do it.Quote:
Originally Posted by virtualrain
Considering the trouble AMD had getting this product to market, Intel was more or less correct it would appear. The whole advantage of Intel's MCM approach is simplicity, yield (costs), and time to market -- all of which has proven to be quite effective so far.
http://www.eetimes.com/news/latest/s...leID=201804316Quote:
"At 65nm the die would be too big to hold four [Intel] cores and it would be so expensive it would not make sense," said Bryant. "Our 45nm process technology will allow us to do a monolithic quad-core design," she added.
Yeah i remember the article with Pat Gelslinger (sp) saying that it was economical to do it for Intel. Maybe 45nm yields are good enough to actually make a monolithic quad core.Quote:
Originally Posted by virtualrain
It would seem that based on the limited time we've seen tick-tock in motion that the ticks's get the monolithic dies and the tocks don't.
Presler was a tick, and dual die dual core.
Conroe was tock and it was monolithic dual core.
Penryn was tick and dual die quad core.
Nehalem is tock and is monolithic quad core.
Because the ticks don't matter as much as the tocks. The ticks are just used to get the manufacturing process mature enough for the tocks.
Although how they're going to do the 8 core Nehalem on the 45nm process and make it affordable is beyond me.
yeah so although it's a die shrink of Merom, it was designed for High-K. The whole point of doing that was so that by the time Nehalem rolled around, the 45nm High-K process was mature enough to make a larger die without taking too big a hit on yields. I don't see how because of that Penryn wasn't designed for High-K dielectrics.Quote:
Originally Posted by Orthogonal
I also heard that the lithography doesn't actually get the transistor to 45nm and that they have to do some etching to get it down to the 45nm mark.
Why would you say that. I am not a member of AMDZone, but i have frequented the site. A few of their poster are far more intelligent than any one here. (no offence intended). Some would refer this site to being far to Intel biased- No big deal though.Quote:
Originally Posted by Movieman
Kindest Regards
Penryn is a shrink of Merom/Conroe, while I suspect there is opportunity to design to the 45 nm strengths, the basic circuit design, transistor expectations, etc. were fundamentally rooted in the 65 nm process technology. Same concept about K8 and 65 nm Brisbane, K8 was initially founded in the 130 nm node.Quote:
Originally Posted by Fuji
The most fascinating thing about Intel's 45 nm technology is the performance of the PMOS, and if you read up in the literature (basic design stuff, the IBM Journal site has some good info there), the ratio of PMOS to NMOS performance affects the overall approach.
For example ... IBM maps out beta, the ratio of PMOS to NMOS as they designed their circuits for the Power 6 (a ground up design)
http://www.research.ibm.com/journal/rd/516/curran.pdf
As such, deisgners fashion the geometry and layout of their transistors with this information in mind. Since Nehalem has gone modular and totally reworked, it is expected the designers will leverage the PMOS performance to the fullest advantage.
This is what Gelsinger meant when he said
I am not sure how Intel will ultimately use this, based on die size, transistor count, etc. Anandtech showed a 10% increase in performance for a much larger total die than current Yorkfield. I suspect they are leveraging it to keep thermals low at the same clock... not sure.Quote:
"The Core micro architecture is built for 45nm and 65nm. In the case of Nehelam, it is natively architected to take full advantage of 45nm,"
"In that sense it is really going unlock the full potential of that process technology's capabilities beyond what the Penryn was capable of doing."
i think i see what you're talking about.
What you're saying is that Intel changed the transistor ratios for Nehalem as opposed to just changing lambda (design rules)?
But wouldn't they have to have changed the L and W for Penryn anyway? For a simple PMOS process, the length of the transistor is determined by first level lithography and the width, second.
So since they nave a 45nm pitch, they would have had to change the L and W anyway. Had they taken Conroe and brought it directly to 45nm, then yeah, you can just change Lambda, but that's not the case.
I guess what i'm wondering is what you wanted me to read on the PDF.
I'm asking all these questions because i'm doing a VLSI lab right now.
More or less... I have made a hobby out of reading and tracking the device physics as the industry as progressed. PMOS is typically a 'slower' transistor (all things being equal) than an NMOS transistor. This is because the majority charge carriers for a PMOS device are holes where as NMOS they are electrons. The effective mass of holes often out weight that of electrons, so the hole mobility tends to be lower (hence slower transistors).Quote:
Originally Posted by Fuji
In short, take what you can get... if your PMOS is weak, then you rework your circuits to use as few PMOS as possible or you account for the difference in the design of the bitcell and transistor geometry (notice the gate length between PMOS and NMOS are different in the IBM paper I referenced above, PMOS being shorter to account for the fact that PMOS is slower)....
It isn't that Intel turned to the beta as a major component, it is that they developed a good PMOS transitor which the Nehalem designers can augment around and take advantage of....
Jack
i thought the mobility of the holes decreased due to the fact that it has to take the area of another hole...or something like that. I don't remember much of device physics.
The mobility also depends on the doping of the region...just thought i'd throw that in there.
So you said that the goal was to use the least amount of PMOS as possible.
However, CMOS is Complementary Metal Oxide Semiconductor which would imply PMOS and NMOS. The whole idea behind CMOS is that both PMOS and NMOS have their strengths. For an Inverter, the PMOS is better with the output high and the NMOS for the output low correct? (it might be reversed). But when you remove PMOS don't you start violating the mere definition of CMOS?
I've never done CMOS processing before so i don't really know it from a physical process standpoint rather more of theoretical from the exposure to it right now.
Understanding the physics of this is hard to explain in a text based forum, people often think of holes as a charged particle, say a positive charge like a proton. This is an incorrect way of thinking about it. The most simplistic form is to think of a hole as a 'missing electron', however, in metals (and semiconductors), electrons are delocalized over the lattice and here is where all heck breaks loose -- it is a difficult concept to wrap your brain around. To be more correct, a hole would be better thought of a somewhat localized region of deficient electron density.Quote:
Originally Posted by Fuji
From this concept we can then begin thinking about dispersion curves with the interaction of holes with the lattice, which because they are less localized than say the electron equivalent, interact differently. The end result is the hole mobility within any given material is less than that of the electron within the same material. Though the dispersion curve for holes lower the mobility, solid state physics has adopted collecting terms into an effective mass... holes have no true mass really, but the behavior of the mobility can be expressed (and naturally falls out) as a mass, which is always larger than electrons. It is easier to move a marble than a bowling ball.
There are many advantages that I have read as to why CMOS is preferred over just NMOS, part in due to what you rhetorical question above ... while I understand the physics, I am not completely well versed on the actual design side ... constructing an inverter in CMOS has an advantage that it consumes much less power overall. (NOTE: I had to cheat to make sure I got this right ... a good text on this subject is Solid State Electronic Devices by B. Streetman and S. Banerjee)
Jack