thx mate :)
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thx mate :)
You are welcome m8.Quote:
Originally Posted by KURTZ
Well there of course might be other reason then instability or limited OC to play with Skews - performance.
Soon I will be testing which skew gave me stability so I will also test at same time if SKEWS has any impact on performance, but I would be very surprised if they would.
Cheers
Thanks alot for the info !!! :up::up::up:Quote:
Originally Posted by seban
With your SKEW settings I managet do get 8*450 from my Q9450 under 1.2vcore On Auto settings I needed 1.25-1.27 vcore for this FSB :clap:.
Thanks again !
With my CPU, a friend of mine managed to get 8*500 ot P5Q-Deluxe, wich is almost the same like my MIIF, but for me is impossible :( Any advices how to tweak the mobo with the system in my signature ?
Here some shots 8*500@1.36 vcore:
http://img162.imageshack.us/img162/3029/3dmv4850yx1.jpg
http://img225.imageshack.us/img225/5595/snm4000hz3.jpg
And some shots on 8*490@1.296 vcore:
http://img520.imageshack.us/img520/2938/q8fa4.jpg
So the CPU can a lot, but I still can't make it stable :(
Would be a nice test... :)Quote:
Originally Posted by seban
Weekend is almost here stay tuned :)Quote:
Originally Posted by JoeBar
Damn this thread is almost dying... All this core i7 threads getting in the way =/ This was / is a very good mobo, I hope you guys keep feeding the thread!
TBH if new Bioses will not introduce working Pull-ins then most of things are covered here.Quote:
Originally Posted by Simps
But I would also be happy to keep it alive.
What exactly does pull-ins do? It wasn't in the manual or anything.
Increases bandwidth / reduces PL LevelQuote:
Originally Posted by shoehorned
What are some Memory Bios options to get some speed up?
Static read control = enabledQuote:
Originally Posted by Gunnz Akimbo
Dram read training = enabled
Ai Clock Twister = strong or stronger
Use the lowest performance level you can
Which ones are more important? I noticed that when setting the Ai Clock Twister on strong or stronger, the PL level needs to be higher, otherwise there's instability or can't boot into windows.Quote:
Originally Posted by CryptiK
In that case you need to increase the vNB to make it stable.
Static read control and dram read training give a nice bandwidth boost, and AI Clock Twister gives a small bandwidth increase but reduces latency.
Performance level is by far the most influential on bandwidth. Set the lowest possible PL, then set the others to whatever you can, increasing vNB to reasonable level to aid stability.
What is considered reasonable? I've had vnb up to 1.50v for 2x1gb sticks, PL 8, and fsb 500.
Dont know your exact specs but 1.50V vNB is pretty high already, just for 2x1gb sticks.Quote:
Originally Posted by shoehorned
Wich ratio you have ? fsb:ram !
Around 1.30 - 1.45v is all you should need. Even with a quad and 2 x 2GB sticks, PL8 and around 430 - 475 FSB.Quote:
Originally Posted by shoehorned
That said though, I thought I was rock stable, but i can't get crysis stable at 4GHz. It's intel burn test stable, 13 hours orthos stable, windows memtest stable, dual SPI32M stable, but it cant last more than 10 minutes in crysis in the heavy scenes, sometimes as little as 30 seconds, before crashing to desktop.
It's definitely not my video card causing the instability. I dropped the system to 3.8GHz (423 x 9) and used the ram at the same speed/timings/voltage as normal, and left the card at the usual speed and voltage, and it was totally stable for 2 hours of gaming.
Increasing the SB 1.1v to 1.2v helped a little, but didnt solve it, I've tried up to 1.3v to no avail, and SB 1.5v makes no diff no matter what I set. Increasing vNB to 1.45v (way overkill for my FSB/ram timings) and it made no difference. Ive tried CPU & NB clock skews between 100 and 300ps, and all ram skew combos to no avail. I've dropped AI Clock Twister to moderate in conjunction with raising vNB and it didn't help either. i tried PL10 (usually run PL8) and it made no difference.
It's actually more stable at 534 FSB and 7.5x MP than at 445 FSB and 9x MP. This is a really odd issue. I'll report back if I can get it sorted, and running a lower cpu speed/FSB is not an option for me, I'll change mobos before I do that. I have a few more things to experiment with, but I've pretty much exhausted all my options.
Have you tried setting PCIE to 101, 102 or 103?Quote:
Originally Posted by CryptiK
I had some major issues with Far Cry2 at 100 and 101. Setting PCIe to 103 resolved my gaming instability.
Something to try if you havent yet.
You could always come to the red side:D The grass isnt always greener on the other side:rofl:
Yeah I have tried all bootable PCI-E freq's and makes no difference. Frustrated, I got crazy and set NB GTL Ref to -100mv and to my abject amazement so far its been stable for an hour in crysis at 4GHz and all my normal settings for everything else. It's very strange as my board seemed to really dislike any NB GTL Ref setting other than auto (it still gets very unstable with any positive NB GTL Refs), but I thought what have I got to lose by trying again. I will have to test other things like IBT and Orthos to see how it behaves.
There is a nice tut from Tony over at OCZ that explains in simple terms CPU Clock Skew and NB Clock Skew, how they work and how/when to adjust.
This from there site
Intel FSB Over Clocking, clock skew and the effects it has on system memory.
This applies to all P35, P43/P45, X38 and X48 based Intel motherboards.
Front side bus has been with us for a few years now, we have all become used to talking “what FSB speed” etc and some bios writers have even chosen to use the FSB string in bios for AMD CPU's as they feel more people understand what FSB does over Hyper transport Bus or HTT. The fact is FSB has limits, especially when the clocks on a motherboard are not as accurate or “clean” as they should be.
Many of the new enthusiast level mother boards now feature some level of user tweakable skew, I actually feel in opening up these options many of the bios/board level tuning engineers have got a little lazy and just left end users to set what used to be programmed in the background.
So what skews do we have access too and how do they work?
On a typical enthusiast level board we may see the following:
1 NB clock skew
2 CPU clock skew
3 Dram clock skew
4 Dram command skew
Working from 1 thru 4 let us have a look what each of these do.
1 NB clock skew and 2 CPU clock skew.
As the CPU has a clock so does the Northbridge, with high speed DDR2 and now even higher speed DDR3 this clock has risen to higher and higher levels, the main issue is the clock that drives the NB as these insane speeds suffers from jitter as the frequency rises. One way round this is to use high specification clocks with high specification power supplies that feed them, the issues with this at the motherboard level are cost and real estate.
On most motherboards NB skew can ONLY be delayed, usually is 100ps steps. Now you would feel that adjusting this clock would be in relation to the CPU clock, the fast is though it seems to follow this rule but not follow it at the same time. In theory you should only have to adjust either the NB skew or the CPU clock skew to bring them into alignment, thru hands on testing both have been found to work well when used together. Using Intel's new dual core processors such as the E8500 CPU most boards seem to respond best to between 300 and 500ps delay skew on the CPU clock from around 1600FSB(400) upwards. What seems to happen is the clock advances as you program an increase in FSB speed, so the clock looks to “drift” so you have to dial it back.
NB clock skew from testing does NOT look to need as much, I have found 100 thru 300ps skew adjust usually can help although it is NOT always needed, it looks to depend on the NB memory controller load. So if you are just running 2x1GB dimms you probably do not need to worry about NB clock skew as much but running 8GB of memory may force you to dial in some adjustment.
3 Dram clock skew.
Most modern desktop enthusiast level motherboards have 4 dimm slots, we “hope” the motherboard designer has calculated all traces from the memory controller to these dimm slots to be exactly the same, the reality is though in most cases they are not. What this means to over clockers is the clock signal arriving at the dimm slots may be different to each dimm just by a few ps. So the purpose of Dram clock skew it to try and re align these clocks across all 4 dimm slots so that they all hit the memory at exactly the same moment.
Here is a quote from Lostcircuits.com where my good friend Michael Schuette has been educating people for many years.
“In a dual channel memory system all data have to arrive at the receiver (memory controller) at the same time. In order to achieve this, it is necessary to adjust the clock skew of the data strobe to take into account the different trace lengths between the memory controller and the corresponding memory slots. Older designs have largely employed snaking of the memory data traces, however, an easier way of getting there is to adjust the data strobes with a differential delay for the two channels. This explains the different timing values for the two memory channels with, for example, the clock skew of channel A being advanced 150 psec further than that of channel B. The physical trace length is different for the two channels and, therefore, the clock skew needs to be adjusted accordingly to compensate. “
http://www.lostcircuits.com/advice/bios3/8.shtml
Now what is frustrating for most of us is we have nothing that shows us a “start point”, modern motherboards do feature a system that “looks” to see where the clock signal should be (DQS Training) so skew at AUTO should be close, the reality though is high speed and high load can push this AUTO feature quite a way out from being close so you may be forced to adopt a “lets see if this works” methodology to your testing unless you happen to have 4 input high speed scopes at your disposal which means you can see the clocks etc and just dial them in. Also bios engineers can hide skew settings behind the AUTO setting which they feel work well, the issue here though is different memory IC brands, batches or die revisions coupled with different PCB have a massive effect on what skew works and where it needs to be, so fine tuning a board for 1 specific brand or type of memory is VERY bad.
What you are faced with is the need to adjust settings end users really should not have to change, it is an ugly situation but noise, jitter, poor component quality, high speed and in some cases a little laziness have forced this upon us.
4 Dram command skew
First we need to understand how Dram Command works:
We all know Command or CPC (command per clock) as 1T or 2T, for Intel systems this is actually 1N and 2N. A command signal is given by the memory controller when it first attempts to access system memory. Basically if you have 1T set the memory controller will try to latch onto a memory bank, the name for this is Chip Select as this is exactly what it is trying to do in 1T clock cycle. Once it has latched it looks for Columns and Rows, we know them as CAS and RAS. CAS or column address strobe and RAS or row address strobe can either take 1 clock / 2 clocks or in some cases 3 clock (3T)
So adding Command skew into the mix means we can advance or delay the memory controllers attempt for that first access to a bank of memory in relation to the data clock. This means we should be able to dial in 1T (1N) performance at higher clocks or with an increased memory load. Using 1T (1N) is usually very dependent on the amount of banks and whether they are single rank or double rank. 4 banks but single rank means 4 modules that are single sided, 4 banks double rank means 4 modules double sided. 1T (1N) works best with single rank modules and easiest of all with just 2 banks (2 modules installed), having Command skew though may allow us to dial in 1T(1N) where it usually will not run, this option however really is for those seeking the absolute max from their systems and being honest most end users would do better sticking with 2T (2N command) and leaving this skew option by AUTO.
Now we need to look at the Front Side Bus its self (keeping it simple)
FSB is Intel's proprietary name for the bus architecture it uses on its current processors. This bus speed is calculated using a bus multiplier and bus frequency. In the case of most processors such as the dual core E8500 or quad core Q9650 this is given using a Front Side Bus of 1333MHZ which is quad pumped so we need to divide by 4 and a bus multiplier which is 9.5 for the E8500 and 9 for the Q9650.
1333MHZ/4=333
333x9.5=3163MHZ E8500 base speed
1333MHZ/4=333
333x9=2997MHZ Q9650 base speed.
Using the available ratio's Intel has built into its memory controller we can adjust the dram speed to either run synchronously with the CPU FSB ( most efficient way) or asynchronously which adds a little extra latency.
There are in fact 2 synchronous options for the memory bus, these are 1:1 and 1:2.
Option 1
1:1 would mean a CPU with a FSB of 1333MHZ would have dram running 333MHZ(single pump clock) X 2 for double data rate which means 667MHZ or PC 5400
Option2
1:2 with the same 1333FSB would mean a base clock of 333MHZ(single pumped clock) x2 for 667 resulting in a dram clock of 667x2 which is 1333MHZ.
Option 1 is normal on DDR2 systems, with Option 2 being available on DDR3 systems. Option 1 is actually available to DDR3 also hence why there are 2 ways to run synchronous.
There are other options for Dram ratio, these usually are all down clocks or up clocks for the dram speed with reference to the single pumped FSB speed. Its important to know that any move away from synchronous clocks will add latency and in such be slightly slower than running synchronously. It is not always best to run very high memory speeds on an Intel system, the architecture for FSB means data has to travel from one domain to another thru the memory controller. This is where tRD or the read delay comes into play (performance level)
Keeping things very simple the memory controller has rules. These rules involve the following.
1 CAS latency on the memory
2 front side bus Strapping in relation to the Northbridge
3 the memory ratio(divider) used
4 the tRD (read delay) you are trying to run.
In the case of DDR3, to physically run a 2000MHZ module at 2000MHZ you have to run 2000FSB. This means a bus speed (single pumped) of 500 set in bios. Now this is a huge overclock for quite a few components.
1 Clock generator
2 Northbridge
3 CPU
4 Memory.
Even a 1600MHZ module will require 1600FSB which for most mainstream processors means over clocking. So again you have the following items running out of spec.
1 Clock generator
2 Northbridge
3 CPU
4 Memory
As mentioned earlier the higher the bus frequency the board is running the more chance you have of jitter or clock misalignment. DDR2 from around 1000MHZ suffers from clock issues on the boards, DDR3 is the same. From around 1200MHZ DDR3 usually needs some tweak to have it working cleanly. For end users this means the following:
1 The higher the memory speed is, the more chance you have of needing to adjust skew
2 The more memory load( number and size of modules) you have the more chance of needing to adjust skew
3 The higher the CPU bus speed, the more chance you will need to adjust CPU clock skew and dram skews to being things back into alignment.
TRD read delay/performance level has a huge effect on how easy a board will run also. It is most important you dial in the exact delay that is needed for the FSB and CAS latency you are running. It is possible to force the memory controller to run with a tighter tRD, this usually involves over voltage of the NB chipset but again this is for end users who are looking to squeeze every last drop of speed from their systems. Motherboard bios engineers usually have dialed in algorithms that set the correct tRD Vs CAS latency selected and the FSB set in bios Vs the memory ratio used. However they do sometimes get it wrong, so be prepared to have to fine tune.
A good article explaining tRD can be found here: http://www.anandtech.com/mb/showdoc.aspx?i=3208&p=5
FSB scaling, how to make it run higher.
Explaining FSB can be a little difficult, I usually like to compare the bus to a cloths line with towels hanging on it on a windy day. The reason for this is as follows.
The CPU, (if a quad core 2 cpu's) are hung on the FSB Just like 1or 2 towels, the NB chipset is also hung on the FSB just like another towel on the cloths line. As the FSB frequency rises liken it to the wind speed getting stronger...the towels have a hard time staying on the line and can get blown off, in our case the limits of FSB are reached and components fail on the bus or just fall off.
So how do we increase resistance to FSB issues as the frequency rises?
In bios we have a few tools that help. These are:
VTT or FSB voltage
GTL voltages both CPU and NB
NB voltage
CPU Vcore
Im not going to explain how these work, its best I link you to some awesome articles that show you their effect. I just need to explain here than you need to make sure you have all items on the FSB as stable as they can physically can be. For you to stand a chance of getting memory running stable on your system FSB stability is critical.
Here are some articles to read:
http://www.thetechrepository.com/showthread.php?t=87
http://www.edgeofstability.com/artic.../gtl/gtl1.html
Now for the less technical amongst you I will break it down into a few brief points you need to know.
1 quad cores do not clock as high on the FSB as dual core CPU's do. The reason for this is an Intel quad is actually 2 cpu's in 1 package, and they have issues staying synced on the FSB
2 The NB reacts just like a CPU does on the FSB, its important that you dial in GTL+ voltages as accurately as you do on the CPU to have it clocking on the FSB well.
3 Clock Jitter has a profound effect on the FSB, cheap boards have cheap clocks, cheap clocks usually mean more Jitter which equal lower FSB overclocking.
4 Always dial in GTL before you adjust VTT (fsb voltage) in many cases an increase in VTT is not needed.
Usual GTL values for dual core and high FSB are (45nm cpus)
0.63%
0.63% for each core
0.61% for the Northbridge
For quad cores as I have used down as low as 0.61% for GTL, it all depends on what VTT is set and what the processor needs. Usually though 0.61% is good for the Northbridge with all CPU's.
Try to keep VTT no higher than 1.3V with 45nm CPU's, more may kill them. Remember GTL % values are based on that % of VTT voltage applied. Some boards have values that may justy have numeric values, 0 to 255 etc, for these boards you must research the common used values and cross reference them against the %Value given to VTT.
Overall staying between 67% and 60% is wise for all 65 and 45nb cpu's
:rolleyes:
Nice find Grnfinger. :clap: :clap:
Heres the link
http://www.ocztechnologyforum.com/fo...ad.php?t=40747
Yeah I have read that guide before when I was new to P45's, it's a good write up.
Im thinking about trying the new bios (1901 or 1902 or something i believe)
Anyone using it and notice a difference at all? Im trying to get 500x8 stable and wondering if it'll do it for me
1901 offers nothing more than 1802 unfortunately
Its a stable bios but zero improvment
Nevermind then.. :(
Still cant get 500x8 stable btw Grn. i had sent you another PM, not sure if you got it :P