Be nice to see if another 2gb kit will let you keep the same clocks greg.m....
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Be nice to see if another 2gb kit will let you keep the same clocks greg.m....
Cant resist asking the following question.
From the M/B Specs that i Google found the following
In an effort to eventually get rid of the conventional IDE ATA standard, the X38 chipset removes IDE support altogether. Despite this, the Maximus Formula ships with a single IDE port thanks to the use of the JMicron JMB368 PATA controller. The ICH9R south bridge offers up to six Serial II ATA ports, boasting data transfer rates of up to 300MB/s. Intel also offers RAID functions for these four SATA ports, supporting RAID 0 for performance and RAID 1 for protection, along with RAID 5 and RAID10. Advanced Host Controller Interface (AHCI) further boosts performance with Native Command Queuing (NCQ), and provides native hot plug for drive swaps.
Now
If the drives them selfs supporting 3Gb/s speed and the MotherBoard it self does the same, Why are is the speed result lower that that?
I know n00b question.. but here you have it.
I need some help with my new memory. I recently bought a set 2 x 2GB Mushkin XP2-8500 (996599). And dont know what would be best for performance. Currently running 9x400 with mem @ 533Mhz 5-5-5-15 but with a 3:4 divider.
My CPU is a soon to be replaced E6850 @ 3,6Ghz/ (3,7Ghz capable). So I can also choose to run them at 8x450 with 1:1 and then try to lower timings and PL, or again with a divider and try to OC the memory. Anyone any idea what would be fastest? Or anyone with other useful tips regarding this memory if I choose to OC? Cant find a lot of users here on XS.
Tnx in advance.
Ok right now put it at 8x460 with my memory @ 1105Mhz 5-5-5-15. Static read enabled, clock twister moderate, PL 9. Running Windows mem test for stability, hope it holds.
Would it be a big help to switch to bios 0803? I'm still on 0410.
Edit:
Ok seems to be stable, of course no big OC but all bits help. Wouldnt 1200Mhz be possible with this mem and lower timings? Can't find any results.
Why do you use PL 9 and not PL 7?
Take a look at Everest Cache Latency & BW at PL9, this should put memory read bandwidth around 5-700mb/s slower than memory write bandwidth correct?
If so you can safely tighten down to PL8, which should close the gap to 2-400mb/sec, and probably not require any additional Vnb, or if so very little. PL7 at that FSB will need too much more Vnb, and too tight of a PL sucks for everyday usage anyway. Stability changes with the weather. One day its too warm and the thing crashes randomly, then you get a cool day and it runs perfect.
Not worth the hassle IMO, it's great for benching but other than that for my every day usage I normally use the next PL lower than the one that gives roughly equal Memory Read and Write bandwidth, which at 460FSB will be PL8. PL7 will give roughly equal read/write, and require a good 0.05-0.10v more on Vnb for consistent stability.
Now personally I've run PL7 at 481FSB on this board, but I was using near 1.53v Vnb and even with this much, sometimes from boot to boot it would be hit and miss. No amount of voltage or fine tuning can fix this period. I ended up dropping down to PL8 because I could run it at 1.47v without it missing a beat. Mind you it would post and even pass stress tests at 1.41v without ever getting an error, but when it came down to real world usage such as long gaming sessions or 24/7 uptime, i needed that extra 0.06v or so to keep the thing from BSOD'ing, leaking memory or just plain old crashing apps randomly. Was it worth the extra 300mb/sec read bandwidth to have it crash after 2 hours of gaming or in the middle of watching a movie, absolutely not. If anything my system actually responded much better from loading up windows, to opening or closing apps, with a slacker Performance Level. PL9 was a bit too slack, and made things no better than PL7.
So to sum it up, don't listen to these clowns when they say a tight PL is the way to go, because they also are the same ones saying they get errors in prime or linpack on settings that were previously stable, and the same ones who won't accept that settings or voltages are too tight or too low to be the problem :up:
Just find the Performance Level that gives you both responsiveness and stability. Try PL9 and PL8, and test both stressing and everyday usage, take note of how windows boots up, time to display icons, load apps, etc. See which of the two suits your settings.
if i have an E8600 and i want it to be a 5ghz with 1.50vcore wich gtl cpu and nb do i need to calibrate it correctly? divisor 1:1 585 x8.5multi or 555x9 multi gtl cpu 63 y nb gtl 67?¿=
eyes i need to spi2m and 3dmark
question, when you run prime,
1- do all cores follow each other
2- some follow some not example 1,2 / 3,4
3- some follow one left behind but only 1-2 passes
4- 3 of them follow each other 1 is always left behind with several passes
while running higher PCI at 109 during prime i noticed that the temps, volt reading etc where flactuating.
pushed up the SB a bit with not much improvement. took it the PCI down to 100 but still the same. will raise the NB again
Edit 1
This is Not happening during Large FFTs but IS happeing during Small FFTs- probably due to the L2 cache-
Edit 2 Lowering Volts on the CPU (currently 1.500V the cores are passing Small FFT in a more "even pace" almost following each other.
This means or i can interprete it as while running with higher volts iam getting the so called CPU throttling
Locigally i should try to get even lower cpu volts and see if this does the trick.
for example at cpu 1.543V i was almost 5:10 meaning core 3 was on test 5 while other cores at 10
Currently running Prime95 with CPU 1.500V iam 5:8 (core 3 at test/pass 5 while the others are at 8)
Here is my results with pcie110 sbv1.10(bios):
http://img269.imageshack.us/img269/9...lipphdtune.jpg
Q9450@3.72GHz and G.SKILL F2-9600CL5D-4GBPI@1239MHz with tRD 6
To get that stable I have to advance the DRAM CLK Skews on Channel A and B with 50ps.
I have to use tREF at 4836T for DDR 1239MHz.
To remove the problem with the CPU and NB Clock Skew I have to bump the CPU Voltage 2 steps in the BIOS than what I normally need for 3.72GHz. I think that the CPU Clock Skew and NB Clock Skew Delay difference of 100ps is to large and that the CPU Clock Skew should be at Delay 150ps instead of Delay 200ps.
Code:Ai Overclock Tuner [Manual]
CPU Ratio Setting [8.0]
FSB Strap to North Bridge [400MHz]
FSB Frequency [465MHz]
PCIE Frequency [100MHz]
DRAM Frequency [1239MHz]
DRAM Command Rate [2N]
DRAM CLK Skew on Channel A/B [Advance 50ps]
DRAM Timing Control [Auto]
DRAM Static Read Control [Enabled]
Ai Clock Twister [Moderate]
Ai Transaction Booster [Manual]
Common Performance Level [06]
Pull-In of CH A/B all disabled
CPU Voltage [1.37500V]
CPU PLL Voltage [1.50V]
North Bridge Voltage [1.41V]
DRAM Voltage [1.88V]
FSB Termination Voltage [1.32V]
South Bridge Voltage [1.05V]
SB 1.5V Voltage [1.50V]
Loadline Calibration [Disabled]
CPU GTL Voltage Reference [0.63X]
NB GTL Voltage Reference [0.67X]
DRAM Controller Voltage REF [Auto]
DRAM Channel A/B Voltage REF [Auto]
CPU Spread Spectrum [Disabled]
PCIE Spread Spectrum [Disabled]
CPU Clock Skew [Delay 200ps]
NB Clock Skew [Delay 100ps]
CPU Ratio Setting [8.0]
C1E Support [Disabled]
CPU TM Function [Enabled]
Vanderpool Technology [Disabled]
Execute Disable Bit [Enabled]
Max CPUID Value Limit [Disabled]
http://i431.photobucket.com/albums/q...D6-LinXEVE.jpg
Because ASUS PC Probe II, EVEREST and RealTemp don't go well together I'm going to run my test again to show you that it's really with these settings and voltages and add a screen shot to this post later.
Just to show you that this "Clown" also knows some magical tricks. :D
http://i431.photobucket.com/albums/q...D6-LinX-BI.jpg
Ok Tnx for the advice, I also thought PL7 to be a bit tight on these speeds but it all seems to be very stable. So I did the everest Benchmark and my read/write bandwidth were 9440/8443. So my Read is actually faster instead of slower. What would be best in my situation?
Also thinking of setting other divider so I can try the 1200Mhz setting, dunno if the mem will hold though, will have to see.
your scores look off, did you have to relax timing to get there
this is on my p45 with no tweaks
http://i237.photobucket.com/albums/f.../1240ram_2.png
Even my X38 scores are higher
1174MHz
http://i237.photobucket.com/albums/f...0_1174BEST.png
1212MHz
http://i237.photobucket.com/albums/f.../TEST4_505.png
Now that my blocks have arrived I will be able to test this board out and compare the two
http://i237.photobucket.com/albums/f...r/DSCF0093.jpg
Of course my score is lower my CPU isn't running at 4GHz+. ;)
This test isn't to see what the highest bandwidth is. This test is to see if it's stable with these settings. Who cares how high the bandwidth is if it isn't stable. :shrug:
ASUS doesn't care if it's stable or not. :D
By looks of it hus bandwidth is cripped slightly from adding extra Advance on DRAM delay skews to pull off PL6 without too much extra Vnb and keep the thing stable. That's my take on it anyhow.
A-Grey,
Not bad mate, good to see you took those clown shoes off and got the thing working a bit better :D
By the way the CPU/NB clock skew delay increment is limited by the resolution achieved through MCHBAR register adjustment which as you imagine is what Intel designed into the MCH. I've never seen a bios use anything but 100ps steps on X48/P45, all vendors alike. This pretty much confirms it is achieved through MCHBAR registers since not all vendors use same clock generator.
Now I don't have the faintest idea where you will find the value, but I have a rough idea. It'll be somewhere between either 000-100h or B00-FFFh. First range looks like it holds initialization values, and the second range contains registers which are used for clock driving/receiving/compensation and GTL+ circuit adjustment, such as MCH slew rate, MCH vref adjustment, GTL buffer strength, Host slew Rate input, etc. So if anything it should be in here.
Basically Asus are stuck with the same adjustment steps that everybody else is. Intel obviously didn't go any higher with resolution because cost to manufacture would go through the roof, and I don't think they'd be able to just say well we gave the overclockers higher resolution clock skew adjustment, so all your chips are now worth $50 more to purchase. They'd have stock that'd never sell :)
Ok did some further testing and stressing. Right now I'm at 1161Mhz via 4:5 divider. This gives me noticable performance boost during boot and normal use.
I tried 1236Mhz aswell with PL9 but it didnt even boot windows, and dont want to give it too much vdimm.
http://img2.pict.com/01/2f/32/01f567...C/800/mem2.jpg
http://img2.pict.com/4e/ed/5e/15ce4a.../L8S5b/mem.jpg
Any ideas how to improve?
If you google a little bit you will find enough pages that can show you that Gigabyte boards have these 50ps clock skew increments, including the X48 Chipset boards. This is probably one of the reasons why it's a lot easier to run at high FSB's on these Gigabyte boards.
I think that ASUS boards don't have them because nobody ever asked for them.
My settings for 8 X 465MHz and DDR 1239MHz with tRD 6 aren't bullet proof. I didn't completely remove the instability I just moved it a little further with raising the CPU Voltage just enough to do 25 passes of LinX. I know that if I do more passes at some point it will fail.
I hope that ASUS is going to see the problem know too and that they change the increments to 50ps.
There's one thing I know. The ASUS Engineer didn't tell me that it isn't possible to have 50ps clock skew increments. There's still a chance that they add it in a new BIOS release and I hope that they add tREF too.
The fact that Gigabyte has 50ps skews means nothing. What has already been said many times getting high fsb on quad + 600mhz on ram + pl6 is no go.
Try to lower PL, increase vDDR, vNB. Don't tell people that 50ps skews are the key while they aren't - you just can't make thing works so fast with so tight timings and so low voltage.