LP UT X48-T3RS, E8600, 500x9, 2x2GB ReaperX 1333MHz, Post 1 Of 3
DFI LP UT X48-T3RS, 07/25 BIOS
E8600
500x8, Memory 1666MHz
2x2GB OCZ DDR3 PC3-10333 OCZ3RPR1333EB4GK
OCZ Core SSD - Operating System
2x Hitachi - Applications/Storage
SAPPHIRE 4870
Yellow Slots Used For Memory
The following settings are the only ones that would allow the board to boot using 400/1333. Any other value resulted in a C1 that required the BIOS to be cleared.
Enhance Addressing - Normal
T2 Dispatch - Disabled
Ch2 Clock Crossing Setting - Auto
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http://www.edgeofstability.com/image...ios/main_s.jpg http://www.edgeofstability.com/image...ios/volt_s.jpg
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http://www.edgeofstability.com/image...s/dram_1_s.jpg http://www.edgeofstability.com/image...s/dram_2_s.jpg
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http://www.edgeofstability.com/image.../clock_1_s.jpg http://www.edgeofstability.com/image.../clock_2_s.jpg
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http://www.edgeofstability.com/image...os/phase_s.jpg http://www.edgeofstability.com/image.../feature_s.jpg
Code:
CPU Feature Page
Thermal Management Control................Enabled
PPM (EIST) Mode...........................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Execute Disable Bit.......................Enabled
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled
Main BIOS Page
Exist Setup Shutdown......................Mode 2
Shutdown After AC Loss....................Disabled
O. C. Fail Retry Counter..................0
CPU Clock Ratio...........................9x
CPU N/2 Ratio.............................Disabled
CPU Clock.................................500 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude.......................800mV
CPU Clock0 Skew...........................100ps
CPU Clock0 Skew...........................0ps
DRAM Speed................................400/1333
PCIE Clock................................100MHz
PCIE Slot Config..........................1X 1X
CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled
SATA Spread Spectrum......................Disabled
Voltage Setting Page
CPU VID Control...........................Auto 1.2450V
CPU VID Special Add Limit.................Disabled
CPU VID Special Add.......................111.57%
DRAM Voltage Control......................1.837V
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.543V
CPU VTT Voltage...........................1.320V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Weak
GTL REF Voltage Control...................Disabled
CPU GTL 1/2 REF Volt......................113
CPU GTL 0/3 REF Volt......................100
North Bridge GTL REF Volt ................100
DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Normal
T2 Dispatch...............................Disabled
Clock Setting Fine Delay..................Listed Below
CAS Latency Time (tCL)....................7
RAS# to CAS# Delay (tRCD).................6
RAS# Precharge (tRP)......................5
Precharge Delay (tRAS)....................24
All Precharge to Act......................Auto
REF to ACT Delay (tRFC)...................Auto
Performance Level.........................8
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................Auto
Rank Write to Read (tWTR).................Auto
ACT to ACT Delay (tRRD)...................Auto
Read to Write Delay (tRDWR)...............Auto
Ranks Write to Write (tWRWR)..............Auto
Ranks Read to Read (tRDRD)................Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................Auto
ALL PRE to Refresh........................Auto
Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto
Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto
Clock Setting Fine Delay Page
DRAM CLK Driving Strength............... Level 6
DRAM Data Driving Strength................Level 8
Ch1 DLL Default Skew Model................Model 0
Ch2 DLL Default Skew Model................Model 0
Fine Delay Step Degree....................5ps
Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current 489ps
DIMM 2 Clock fine delay...................Current 489ps
DIMM 1 Control fine delay.................Current 434ps
DIMM 2 Control fine delay.................Current 473ps
Ch 1 Command fine delay...................Current 205ps
Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current 686ps
DIMM 4 Clock fine delay...................Current 686ps
DIMM 3 Control fine delay.................Current 607ps
DIMM 4 Control fine delay.................Current 654ps
Ch 2 Command fine delay...................Current 182ps
Ch1Ch2 CommonClock Setting................More Aggresive
Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto
Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto
Common CMD to CS Timing...................1N
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http://www.edgeofstability.com/image...mtest_64_s.jpg
LP UT X48-T3RS, E8600, 500x9, 2x2GB ReaperX 1333MHz, Post 2 Of 3
LP UT X48-T3RS, E8600, 500x9, 2x2GB ReaperX 1333MHz, Post 3 Of 3