What to Expect From AMD at ISSCC 2011

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02-20-2011, 06:15 AM
undone

What to Expect From AMD at ISSCC 2011

http://blogs.amd.com/work/2011/02/18...at-isscc-2011/

Quote:

* Design Solutions for the “Bulldozer” 32nm: Showcasing AMD’s 32nm technology and leading-edge design techniques, this session will discuss the power savings, performance improvements and new competitive features offered up by “Bulldozer”. Session date and time: Monday, 2/21, 3:15 p.m.

* 40-Entry Unified Out-of-Order Scheduler and Integer Execution Unit for the AMD “Bulldozer”: This session will be used to dive even further into the Bulldozer architecture to understand its out-of-order execution set and how the integer unit performs. Session date and time: Monday, 2/21, 3:45 p.m.

* An 8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing: Interested in the technical and design details of “Orochi,” AMD’s upcoming high-end desktop and server processor? This session will discuss the new technologies and power-saving features used in the design. Session date and time: Tuesday, 2/22, 2:30 p.m.

* A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computer Devices: This session will look at AMD’s first generation Fusion processor, the AMD E-Series APU, formerly codenamed “Zacate,” which combines the power of an x86 CPU and AMD RadeonTM graphics manufactured on a 40nm die. You’ll learn how it was designed and how to optimize performance and energy usage. Session date and time: Tuesday, 2/22, 4:15 p.m.

UPDATE: Bulldozer module shot(compared with Westmere)

http://i54.tinypic.com/vxgmiw.jpg

UPDATE 2: Bulldozer Module VS Magny-Cours

http://www.computerbase.de/bildstrecke/33300/2/

http://pics.computerbase.de/3/3/3/0/0/4.jpg

UPDATE 3:

Hiroshige Goto has a nice photo about bulldozer, maybe more accurate than ever.(Article is in Japanese:confused:)

http://pc.watch.impress.co.jp/docs/c...01_430044.html

http://pc.watch.impress.co.jp/img/pc.../430/044/1.jpg
02-20-2011, 06:32 AM
zalbard

Woah, nice! Looks like we'll find out a lot about BD's architecture and performance from ISSCC 2011!
Which is... starting today and running for 4 days! :D
02-20-2011, 07:08 AM
cesariuth

http://www.miracd.com/ISSCC2011/WebA...P_Session4.pdf
02-20-2011, 07:29 AM
Nintendork

I'm ready.
02-20-2011, 08:31 AM
god_43

i doubt you will see any performance numbers until much closer to launch. but this is still nice and tomorrow we will learn more about the dragons innards.
02-20-2011, 08:36 AM
zalbard

Quote:

Originally Posted by god_43

i doubt you will see any performance numbers until much closer to launch. but this is still nice and tomorrow we will learn more about the dragons innards.

Not according to the OP...

Quote:

* Design Solutions for the “Bulldozer” 32nm: Showcasing AMD’s 32nm technology and leading-edge design techniques, this session will discuss the power savings, performance improvements and new competitive features offered up by “Bulldozer”. Session date and time: Monday, 2/21, 3:15 p.m.
02-20-2011, 10:06 AM
Salsoolo

^improvements ok
but he said numbers :D
02-20-2011, 10:20 AM
zalbard

Current numbers x BD improvements = Actual BD numbers
:D
02-20-2011, 10:34 AM
FischOderAal

Quote:

Originally Posted by zalbard

Current numbers x BD improvements - marketing bias = Actual BD numbers
:D

Fixed ;)
02-20-2011, 11:13 AM
Shadov

Again I doubt you will see *any* numbers, so dont get your hopes up.

Though I hope Dresdenboy and Hans will comment on the design... :D
02-20-2011, 11:15 AM
Manicdan

i expect a few bar charts with fading bars
02-20-2011, 11:40 AM
madcho

Quote:

4.5 design Solutions for the Bulldozer 32nm Soi 2-core processor 3:15 pM
Module in an 8-core cpu
T. Fischer1, S. Arekapudi2, E. Busta1, C. Dietz3, M. Golden2, S. Hilker2, A. Horiuchi1, K. A. Hurd1,
D. Johnson1, H. McIntyre2, S. Naffziger1, J. Vinh2, J. White4, K. Wilcox4
1AMD, Fort Collins, CO
2AMD, Sunnyvale, CA
3AMD, Austin, TX
4AMD, Boxborough, MA
The Bulldozer 2-core CPU module contains 213M transistors in an 11-metal layer 32nm high-k metalgate
SOI CMOS process and is designed to operate from 0.8 to 1.3V. This micro-architecture improves
performance and frequency while reducing area and power over a previous AMD x86-64 CPU in the
same process. The design reduces the number of gates/cycle relative to prior designs, achieving
3.5GHz+ operation in an area (including 2MB L2 cache) of 30.9mm2.
4.6 40-entry unified out-of-order Scheduler and integer execution unit 3:45 pM
for the aMd Bulldozer x86-64 core
M. Golden, S. Arekapudi, J. Vinh
AMD, Sunnyvale, CA
A 40-instruction out-of-order scheduler issues four operations per cycle and supports single-cycle operation
wakeup. The integer execution unit supports single-cycle bypass between four functional
units. Critical paths are implemented without exotic circuit techniques or heavy reliance on full-custom
design. Architectural choices minimize power consumption.

213M per module, so 852M for a quad module without L3 and northbridge...

so it's around 1.4b-1.5b

And frequency 3.5ghz+ ...
02-20-2011, 11:55 AM
ohnoitseddy

Well, they say that a single module is 3.5 GHz capable. ;) That's the difference between ISSCC and a marketing presentation: it's about the technology, not the end product. That they'll tell you it can run at 3.5 GHz doesn't mean the end product will, certainly not if a chip has four of those modules and is TDP (and yield) limited.

Not saying BD won't, just that you can't draw any conclusions from this.
02-20-2011, 12:03 PM
Manicdan

the 0.8 - 1.3v is interesting, since i would expect them to say the maximum voltage used by turbo.

could this mean it runs on ~1.1v for all cores and turbo is 1.3v?
02-20-2011, 12:24 PM
FlanK3r

think its possible...cause my Thuban can with 1.3V up to 3.95 GHz aircooled :), so with 32nm will see no problem
02-20-2011, 01:06 PM
BrowncoatGR

Quote:

Originally Posted by zalbard

Not according to the OP...

I think its far more likely they'll talk about transistor performance rather than chip performance ;)
02-20-2011, 01:24 PM
[XC] Oj101

Quote:

Originally Posted by FlanK3r

think its possible...cause my Thuban can with 1.3V up to 3.95 GHz aircooled :), so with 32nm will see no problem

Surely that's not stable? I need 1.525v for 3.9GHz stable :(
02-20-2011, 04:10 PM
generics_user

i don't know what to expect from these presentations but i doubt that we're going to get some real new info or performance numbers

OT:

Quote:

Originally Posted by [XC] Oj101

Surely that's not stable? I need 1.525v for 3.9GHz stable :(

seems like you have a dud...

it took VID + 0.1v to get my 1055T to 3.9ghz air cooled on a TRUE

that is with 2.8ghz NB and 4x 2gb of RAM

if you have some ECO sticks try to up the ram voltage a bit, this seems to help alot with memory stability on higher NB clocks and max HT link, this raised my max HT from 280 to 315 mhz (1.5v ram to 1.65) despite running way below the mem limits

additionally higher volts are not always the way to go on a 1055T, i noticed a negative effect from a too high NB and HT link voltage which required more volts on the core to reach a certain speed limit
02-20-2011, 04:32 PM
saaya

Quote:

* 40-Entry Unified Out-of-Order Scheduler and Integer Execution Unit for the AMD “Bulldozer”:

Just curious, unless amd actually starts building heavy construction gear, isn't the use of THE improper in this sentence?

Can't wait to hear more about bd!
02-20-2011, 04:54 PM
BeepBeep2

What I pulled from that (if I'm right)

8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing
3.5GHz+ operation in an area (including 2MB L2 cache)

That's 1MB L3 per core, 256 kb L2 per core...down from 1MB L3 per core and 512kb L2 per core with Phenom II and it's way behind Westmere-EX and it's whopping 30MB of cache...
02-20-2011, 05:09 PM
Kej

Quote:

Originally Posted by BeepBeep2

What I pulled from that (if I'm right)

8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing
3.5GHz+ operation in an area (including 2MB L2 cache)

That's 1MB L3 per core, 256 kb L2 per core...down from 1MB L3 per core and 512kb L2 per core with Phenom II and it's way behind Westmere-EX and it's whopping 30MB of cache...

Make that 2MB lvl2/module (2 cores), for a total of 8MB lvl2 cache on a 4 module CPU. :)
02-20-2011, 07:58 PM
god_43

Quote:

Originally Posted by BeepBeep2

What I pulled from that (if I'm right)

8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing
3.5GHz+ operation in an area (including 2MB L2 cache)

That's 1MB L3 per core, 256 kb L2 per core...down from 1MB L3 per core and 512kb L2 per core with Phenom II and it's way behind Westmere-EX and it's whopping 30MB of cache...

dont forget this is a pretty radical design compared to the intel. perhaps it does not need as much cache as westmere; or does not benefit very much from having more cache?
02-20-2011, 08:15 PM
demonkevy666

Quote:

Originally Posted by madcho

213M per module, so 852M for a quad module without L3 and northbridge...

so it's around 1.4b-1.5b

And frequency 3.5ghz+ ...

best part of this is

Quote:

AMD’s upcoming high-end desktop

not mid range.
02-20-2011, 08:32 PM
LightSpeed

Quote:

Originally Posted by demonkevy666

best part of this is

Quote:

AMD’s upcoming high-end desktop

not mid range.

Well, it may be AMD's high end desktop, like current Thubans are. But I hope to god that it gives SB a run for its money.
02-20-2011, 08:35 PM
Johnny87au

gahh wheres llano?? screw zacate bring on llano/ontario :D

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