Intel TAT / CoreTemp / IDCC all different temperatures....

[fgw]

Originally Posted by psy4fun

Elsewhere, 85C is not an absolute value. Recall what fgw said to best understand:

So, throttling can occur at 85C or something else.

Alex

you got it! the way coretemp works, throttling occurs at the point where one of the cores shows exactly the same value as is displayed as tjunction in coretemp. this might be any other value in programs reading their temperature off the thermal diode. i assume rmclock does so, as rmclock shows slightly different values than coretemp.
but nobody can tell if this temperature displayed in coretemp as 85c is actually 85c, 83c, 88c, or even near 100c (assuming coretemp is using the wrong tjunction) ...
you see, playing around with absolute temps leads nowhere. thats, why i requested The Coolest to implement displaying plain dts values in coretemp. was not able to verify this yet.

[GGuyZ]

Originally Posted by SLi_dog

Technically it's not a "fix" just an adjustment of the Tjunction value from 85C to 100c for E4300s which will mean CoreTemp will read 15C hotter now.

Does anyone know what the Tjunction value should be for E4300s?

This does not make sense at all. Since Tjunction temperature does not exist in desktop processors, why would a fix be required? If you are already assuming that a Tjunction temperature exists(which is fault assumption too, as we all agreed), why not use the same Tjunction for E4xxx as well as E6xxx. I can understand why reporting C2Qs as 100c Tjunction makes sense, but I don't understand this logic with the E4300.

This would confuse many users that will now believe their E4300 operates at a much higher temperature. If any fix was to be applied, then it should be on TAT itself. Or instead, reporting only the DTS value(as fgw suggested) might be a better solution.

Originally Posted by cadaveca

In RD600 cpu throtlles @ 85c via smartguardian. Shutdown temp set in bios also reads same temp. this is not the same temp that Coretemp displays(61c).

So, unless it's the bios @ fault on RD600, Coretemp is not reading correctly. I have same issue too, reading 19c idle in 25c ambient, using AIRCOOLING.

this being said, coretemp reports same temp across many different boards for same cpu, when voltages/cooling are the same. Although the temp may not be perfectly accurate, it's the best we got ATM.

This is very fishy and may damage the integrity of the conclusions which we all now believe in. While the absolute temp reading CT gives may be incorrect in many cases, it should always start throttling at 85C with C2D cpus, and 100C on C2Q cpus and some E4xxx. Obviously this is not real temperature, but it does indicate the throttling point. If this is indeed so, how is it possible that this guy encountered throttling at 61c in Coretemp?

[fgw]

Originally Posted by SLi_dog

Does anyone know what the Tjunction value should be for E4300s?

no, nobody does! the only way to find out is to push this cpu to its limits and see what temps are reported by coretemp when throttling starts...

Originally Posted by GGuyZ

Originally Posted by SLi_dog
Technically it's not a "fix" just an adjustment of the Tjunction value from 85C to 100c for E4300s which will mean CoreTemp will read 15C hotter now.

This does not make sense at all. Since Tjunction temperature does not exist in desktop processors, why would a fix be required? If you are already assuming that a Tjunction temperature exists(which is fault assumption too, as we all agreed), why not use the same Tjunction for E4xxx as well as E6xxx. I can understand why reporting C2Qs as 100c Tjunction makes sense, but I don't understand this logic with the E4300.

most of the time PROCHOT# (TCC activation) temperature erroneous gets referenced as tjunction! coretemp uses this TCC activation temperature as a reference point to calculate temperatures from. TCC activation temperature can't be read by software, BUT there is a bit in a register (we discussed this a few posts earlier) which was implemented by intel. this bit is valid on mobile processors and defines if TCC activation temperature is near 85c or near 100c! i use the term "near" because in reality, this temperature is calibrated on a processor basis and differs from die to die. on one processor die it might be 87c while on an other processor die it might be 83c! coretemp, as i assume all other programs using DTS, uses this bit to decide if for a certain processor 85c or 100c has to be used in the calculations. although this is valid only for mobile processors, this seems to work also for most current BUT not all desktop processors too. we have seen more and more new processors coming out where this assumption is not correct anymore. thats the situations, where coretemp reads temps about 15c off!
so, to get coretemp back to more valid readings, the only thing to to is to change the reference temp from 85c to 100c instead on relying on the obviously wrong set bit in the register. that was done in coretemp 0.95 for e4300 and may be some other processors too.

This would confuse many users that will now believe their E4300 operates at a much higher temperature. If any fix was to be applied, then it should be on TAT itself. Or instead, reporting only the DTS value(as fgw suggested) might be a better solution.

well, in fact the new 15c higher readings might be the correct readings. i have a second rig with one of this e4300. unfortunately i have not yet pushed it into throttling. this is the only way to figure out which temp is right. for now i would assume the "new" 15c higher reading is correct. i can hardly believe, that my e4300 running on air keeps temps at 55c under full load! its far more realistic, that it should read 70c instead. will verify this as soon as i get my hands on this rig ...

Originally Posted by cadaveca
In RD600 cpu throtlles @ 85c via smartguardian. Shutdown temp set in bios also reads same temp. this is not the same temp that Coretemp displays(61c).

So, unless it's the bios @ fault on RD600, Coretemp is not reading correctly. I have same issue too, reading 19c idle in 25c ambient, using AIRCOOLING.

this being said, coretemp reports same temp across many different boards for same cpu, when voltages/cooling are the same. Although the temp may not be perfectly accurate, it's the best we got ATM.

This is very fishy and may damage the integrity of the conclusions which we all now believe in. While the absolute temp reading CT gives may be incorrect in many cases, it should always start throttling at 85C with C2D cpus, and 100C on C2Q cpus and some E4xxx. Obviously this is not real temperature, but it does indicate the throttling point. If this is indeed so, how is it possible that this guy encountered throttling at 61c in Coretemp?

unfortunately i don't have any information on smartguardian and so cant say anything here. you are right, this does not fit very well into this picture. different polling intervals might play a role here.

cadaveca, did the cpu throttle at 85c or did the bios shutdown the system as the bios is set to 85c too? may be smartguardian did not signal throttling correctly? there is a tool called rmclock, which i use to check throttling. may be you can give it a try http://cpu.rightmark.org/products/rmclock.shtml

[GGuyZ]

Originally Posted by fgw

most of the time PROCHOT# (TCC activation) temperature erroneous gets referenced as tjunction! coretemp uses this TCC activation temperature as a reference point to calculate temperatures from. TCC activation temperature can't be read by software, BUT there is a bit in a register (we discussed this a few posts earlier) which was implemented by intel. this bit is valid on mobile processors and defines if TCC activation temperature is near 85c or near 100c! i use the term "near" because in reality, this temperature is calibrated on a processor basis and differs from die to die. on one processor die it might be 87c while on an other processor die it might be 83c! coretemp, as i assume all other programs using DTS, uses this bit to decide if for a certain processor 85c or 100c has to be used in the calculations. although this is valid only for mobile processors, this seems to work also for most current BUT not all desktop processors too. we have seen more and more new processors coming out where this assumption is not correct anymore. thats the situations, where coretemp reads temps about 15c off!
so, to get coretemp back to more valid readings, the only thing to to is to change the reference temp from 85c to 100c instead on relying on the obviously wrong set bit in the register. that was done in coretemp 0.95 for e4300 and may be some other processors too.

You probably did not understand me correctly. First, where did you read that Tjunction is calibrated specifically for each processor. This does make sense, and while I'm aware that PROCHOT# and THERMTRIP# temps are calibrated in the making process, I'm uncertain the same applies to Tjunction. The reason I'm uncertain of this is because the MSR bit you were talking about(bit 30 of MSR 0xEE to be exact), have held constant information(either 85C or 100C as you mentioned) in the mobile processors.

Second, this bit may be valid in many desktop processors, but it has no official reference in Intel docs! It is possible that this bit information has been left by mistake, but it has no real use. Why am I saying this? Well, because in the intel dev forum it has been made clear that trying to derive the real temp from the pseudo Tjunction Temp is wrong. What I don't understand is why the CoreTemp program developer keeps following this mistake, while he knows this unfortunate fact.

Originally Posted by fgw

well, in fact the new 15c higher readings might be the correct readings. i have a second rig with one of this e4300. unfortunately i have not yet pushed it into throttling. this is the only way to figure out which temp is right. for now i would assume the "new" 15c higher reading is correct. i can hardly believe, that my e4300 running on air keeps temps at 55c under full load! its far more realistic, that it should read 70c instead. will verify this as soon as i get my hands on this rig ...

throttling tests cannot help much in determining whether the CoreTemp reading is closer to reality when calculating 100c or 85c. In the previous case, throttling would have started at around 85C core temp. Now it will require 100C to begin throttling, but this has no indication on real temps.

Originally Posted by fgw

unfortunately i don't have any information on smartguardian and so cant say anything here. you are right, this does not fit very well into this picture. different polling intervals might play a role here.

cadaveca, did the cpu throttle at 85c or did the bios shutdown the system as the bios is set to 85c too? may be smartguardian did not signal throttling correctly? there is a tool called rmclock, which i use to check throttling. may be you can give it a try http://cpu.rightmark.org/products/rmclock.shtml

I'm very interested in this as well.

[joebuffalo]

I am totally onboard. Who cares what the absolute temperature is. It requires us to guess what the 'tjunction' is set at. But we do know, without any guessing, what the 'delta to tjunction' is thanks to Core Temp 0.95. So that's what we should be looking at, yeah.

Riddle me this, though. How small can we let that delta get before we are pushing it? Does anybody have any recommendations for how close is too close for a load (100% TAT load) temperature?

[fgw]

Originally Posted by joebuffalo

I am totally onboard. Who cares what the absolute temperature is. It requires us to guess what the 'tjunction' is set at. But we do know, without any guessing, what the 'delta to tjunction' is thanks to Core Temp 0.95. So that's what we should be looking at, yeah.

i see we are talking the same language ...

Riddle me this, though. How small can we let that delta get before we are pushing it? Does anybody have any recommendations for how close is too close for a load (100% TAT load) temperature?

well, i will handle it this way:

• i don't want my processor to start throttling -> keeping dts readings greater 0 would be enough in this case! you might add some safety margin, lets say 10c or 15c, just in case. this would be fine as long as the processor is not overclocked or better said as long as vcore is at default setting.
  
• as soon as vcore is raised, this might be a little different: some time ago, i have read a story on thg about extreme overclocking and there was this link to the physics behind electromigration. don't want to comment on the thg story as i have the feeling they did not interpret it right, and also don't want to warm up old dishes again, but to make a long story short and if i understood the readings correctly: if vcore is increased, current flow increases and thus does current density. double the currentdensity requires 20c lower temps to NOT run into increased electromigration! currently i'm running a vcore of 1.50v and coretemp 0.94 (unfortunately 0.95 fails on my system) reads 50c to 55c under full load. this would translate to a dts reading in the range of 30c to 35c and seems sufficient to me.

[joebuffalo]

Wow, you must have some great cooling going on there.

What are you using to load your system?

I am running an e4300 at 2.8-GHz with a Ninja/Yate Loon cooler and I'm getting DTS readings of about 30 when loaded with TAT.

[fgw]

Originally Posted by joebuffalo

Wow, you must have some great cooling going on there.

What are you using to load your system?

I am running an e4300 at 2.8-GHz with a Ninja/Yate Loon cooler and I'm getting DTS readings of about 30 when loaded with TAT.

dont forget i'm on water!

i use orthos to load my system. small ffts to produce maximum heat and blend test to verify stability. currently running some blend tests at various vcore settings.

regarding your e4300: in a second rig i have an aw9d-max/e4300 running on air with a tt big type 120vx. the e4300 definitely tends to run hotter. have not tried coretemp 095 here as this version crashes my ab9quadgt/e6400 system. seems you are using coretemp 095 successfully. can you post screenshots or just the different readings (temp, dts, tjunction, cpuid, revision, processor) of coretemp 094 and 095? in coretemp 094 temps on the e4300 are going up to 70c. this would translate to dts readings of 15c! if i'm right coretemp 95 should read about 85c in the same situation.

also what voltage do use on the e4300?

[joebuffalo]

Originally Posted by fgw

dont forget i'm on water!

i use orthos to load my system. small ffts to produce maximum heat and blend test to verify stability. currently running some blend tests at various vcore settings.

regarding your e4300: in a second rig i have an aw9d-max/e4300 running on air with a tt big type 120vx. the e4300 definitely tends to run hotter. have not tried coretemp 095 here as this version crashes my ab9quadgt/e6400 system. seems you are using coretemp 095 successfully. can you post screenshots or just the different readings (temp, dts, tjunction, cpuid, revision, processor) of coretemp 094 and 095? in coretemp 094 temps on the e4300 are going up to 70c. this would translate to dts readings of 15c! if i'm right coretemp 95 should read about 85c in the same situation.

also what voltage do use on the e4300?

haha...your cooling is listed right there in your sig...I was just too tired to nitice I guess.

These screenshots are at idle, 60% TAT load, and 100% TAT load.

I'm at stock voltage, 1.325-V

[GGuyZ]

Obviously, all of those who know the logic behind this mechanism will use the Delta temp and not the absolute temp.

But still, getting closer to 'the truth' behind this is intriguing to say the least. I'm especially curious, why did CoreTemp v0.95 decided to change L2 rev chips Tjunction temp to 100c? Where was this logic derived from? It doesn't make much sense because as we can see it seems that L2 chips are much much hotter. If it's a newer revision, going through the same manufactoring process, why is it significally hotter? I can understand ~5c. but not 15c.

[joebuffalo]

To match the results displayed via TAT. Obviously TAT is assuming a Tjunction_max of 100.

[fgw]

Originally Posted by joebuffalo

... your screenshots ...

thanks for your screenshots. can't use tat on my board and coretemp 0.95 doesn't work either ...
from looking at your screenshots: thats what i have expected.

Originally Posted by GGuyZ

Obviously, all of those who know the logic behind this mechanism will use the Delta temp and not the absolute temp.

But still, getting closer to 'the truth' behind this is intriguing to say the least. I'm especially curious, why did CoreTemp v0.95 decided to change L2 rev chips Tjunction temp to 100c? Where was this logic derived from? It doesn't make much sense because as we can see it seems that L2 chips are much much hotter. If it's a newer revision, going through the same manufactoring process, why is it significally hotter? I can understand ~5c. but not 15c.

guess the assumption here is, tjunction could be either 85c or 100c and as 85c was obviously to low it must have been 100c then!
btw. from reading your post at the coretemp forum i have seen you also followed the thread at the intel software network forum...

Originally Posted by joebuffalo

To match the results displayed via TAT. Obviously TAT is assuming a Tjunction_max of 100.

the point, as we all know in the meantime, is tat was designed for mobile processors only! the use on desktop processors might produce results that look right but nobody knows if they are. i really doubt it.
from all what i have read on this so far:

• the decision if 85c or 100c are to be used, based on a single bit in a msr, is not valid for desktop processors and thus wrong.
• even on desktop processors the temp is not exactly 85c or 100c. its just some where near this point.
• this temp is calibrated on a per chip basis and thus different from die to die.
• there is no way to read this temperature by software
• the only reliable way is to use the dts value directly

although not that precise you can use a monitoring program that's reading the thermal diode. comparing this readings to coretemp readings while the processor is forced into throttling. this could give an idea about the value of tjunction. in fact its not tjunction, its the temp where thermal control circuit gets activated, but thats a different story. at least you can figure out if its near 85c or near 100c ...
i tried this on my e6400. throttling kicked in at coretemp readings near 85c. don't remember the correct value. might have been 86c or 87c, but it definitely was not 100c!

[joebuffalo]

Dude ran his e4300 up to 97-C (according to TAT) before he encountered throttling.

http://forumz.tomshardware.com/hardw...ict230942.html

Obviously TAT is GREAT for putting max load on CPUs. But it is terrible for reading temperatures because it was not made for desktops and we have no idea what Tj_max it is assuming when it calculates an absolute temperature. Long live DTS!

[unclewebb]

ted3: Sorry man, thats not throttling.

When I brought my E6400 up to 85C it was definitely throttling. On the Intel C2D there are two types of throttling.

http://www.intel.com/design/processo...als/253668.pdf
Here's a quote from page 13-5 of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Vol. 3A:

"One mode modulates the clock duty cycle; the second mode changes the processor’s frequency. Both modes are used to control the core temperature of the processor."

When a C2D processor first starts to approach Tmax the duty cycle will be reduced from 100% to 87.5%, 75% and continuing down to 12.5% in 12.5% increments. If the temperature of the processor still can't be controlled then the second mode kicks in which reduces the processor frequency (MHz) like you experienced. The first "duty cycle" throttling happens approximately 3C or 4C before Tmax.

My testing has shown that CoreTemp 0.95 which uses a Tjunction of 100C for the E4300 is reporting the temperature correctly.

Rather than take a processor up to the boiling point I decided to do the opposite. I set out to try and run the processor as cool as possible.

To do this I dropped the FSB to 266 MHz ( 200 MHz for the E4300 ), I dropped the multi to 6X and then I also dropped the core voltage down to 1.175 volts. I booted up and set the Intel CPU fan at full speed to cool the processor as much as possible.

At idle I was able to get my E6400 down to 2C - 3C above ambient temperature which makes sense. A C2D puts out minimal heat at idle and even the OEM cooler is sufficient to dissipate that heat.

When I did a similar test on an E4300, CoreTemp 0.94 was reporting the core temperature significantly below ambient temperature which is impossible. An air cooled processor can't be running cooler than the surrounding air so this is a sign that CoreTemp 0.94 was reading too low.

By this test, the 15C correction introduced with CoreTemp 0.95 is correct for the E4300.

It would be interesting to see if anyone else can duplicate these numbers. This is the best and safest way I've found so far to prove that a software monitoring program is wrong.

CoreTemp 0.95 seems to be the most accurate program to date. If you don't believe the absolute value reported then just switch it to "Show Delta to Tjunction temp". I like to leave at least 10C to 15C of headroom to Tmax for maximum performance and stability.

[joebuffalo]

The Tjmax for nay core 2 chip is not necessarily 85 or 100 exactly. It is calibrated for each chip at the factory. That's why the DTS reading is so damn awesome.

And I *think* you weren't throttling. In the Intel docs, it states that the DTS reading is the number of degrees between the current core temp and TCC (throttling). So unless you see a DTS of 0 in CoreTemp 0.95 you shouldn't be throttling. I think. (And since you said you were at 85 degrees, that's somthing like 10 or 20 degrees DTS) Maybe I misunderstood something.

[SLi_dog]

Originally Posted by GGuyZ

This does not make sense at all. Since Tjunction temperature does not exist in desktop processors, why would a fix be required? If you are already assuming that a Tjunction temperature exists(which is fault assumption too, as we all agreed), why not use the same Tjunction for E4xxx as well as E6xxx. I can understand why reporting C2Qs as 100c Tjunction makes sense, but I don't understand this logic with the E4300.

This would confuse many users that will now believe their E4300 operates at a much higher temperature. If any fix was to be applied, then it should be on TAT itself. Or instead, reporting only the DTS value(as fgw suggested) might be a better solution.

I supposed you have to ask yourself what's more believable, allendale core CPUs (E4300 or L2 E63/6400) that idle at or below ambient temperature or that the "reference" Tjunction value for them needs a +15C adjustment?

Anyway, isn't it just a reference value which gives a far better idea of CPU temperatures than we've ever had before to better maintain optimal performance when overclocking? Who really cares if it's 100% accurate?

[unclewebb]

Originally Posted by joebuffalo

The Tjmax for nay core 2 chip is not necessarily 85 or 100 exactly.

Is there any documentation from Intel or any evidence from other users to support that? I'm not saying it's not true. I'm just interested like everyone else in what's really going on.

For my E6400 Revision B2, CoreTemp uses this formula:
reported temp = 85 - DTS

CoreTemp reports 85C when DTS equals zero.

During testing, TAT first started to report, "Thermal Monitor Active" in red for Core0 when DTS was at 2 so CoreTemp was reporting 83C. At this point the reported MHz is not yet reduced but the performance of the processor starts getting reduced internally to try and control the temps. CPUz will still be reporting full MHz but performance is reduced.

If the temperature of the processor can still not be controlled using this first thermal throttling technique, then the processor MHz will also be reduced. If the temperature still can't be controlled then finally the "catastrophic shutdown detector" is enabled and the processor shuts down.

Both methods of throttling will result in reduced performance for your processor. At stage 1, the reported MHz might still show your CPU at full speed but performance is already being reduced.

[unclewebb]

Originally Posted by GGuyZ

....why did CoreTemp v0.95 decided to change L2 rev chips Tjunction temp to 100c? .......as we can see it seems that L2 chips are much much hotter. If it's a newer revision, going through the same manufactoring process, why is it significally hotter?

The reason Tjunction or Tmax was raised from 85C to 100C for the E4300 isn't because the E4300 puts out any more heat or runs hotter than previous C2D chips. A chip built on the same manufacturing process, being supplied the same voltage and running at the same frequency is going to put out pretty much the same heat as previous C2D processors.

Intel raised the maximum so this chip can run 15C hotter before thermal throttling will take place.

The E4300 is designed as a budget chip which will be used in small budget computers that typically have poor air flow and system cooling. This chip gives computer manufacturers more head room to design a small computer without having to worry about the processor hitting the thermal throttle and slowing down performance.

[joebuffalo]

Originally Posted by unclewebb

For my E6400 Revision B2, CoreTemp uses this formula:
reported temp = 85 - DTS

Mea culpa. Sometimes I forget that not everybody has an e4300.

Originally Posted by unclewebb

Is there any documentation from Intel or any evidence from other users to support that? I'm not saying it's not true. I'm just interested like everyone else in what's really going on.

I *thought* I read that in the spec sheets somewhere, but I can't seem to find it in my notes. Maybe I just read it on a forum? I did find this:

http://documents.irevues.inist.fr/bi...79/1/TMI23.pdf

"The DTS is calibrated at manufacturing conditions and the reference point is set to this test temperature. Functionality, electrical specifications and reliability commitments are guaranteed at maximum Tj as measured by the DTS. Any test inaccuracy or parameters variance are already accounted for in the DTS set point."

Which sort implies what I claimed, but certainly doesn't say it clearly. Either way, the paper is a good read.

[unclewebb]

Originally Posted by joebuffalo

"The DTS is calibrated at manufacturing conditions and the reference point is set to this test temperature. Functionality, electrical specifications and reliability commitments are guaranteed at maximum Tj as measured by the DTS. Any test inaccuracy or parameters variance are already accounted for in the DTS set point."

I read the above paragraph and of course came to the opposite conclusion.

I think if Intel is making a batch of processors with a Tjmax of 85C then they calibrate the DTS during manufacturing so that it reads 0 when the hottest point in the core is at exactly 85C. Same thing for the E4300 at 100C. This happens at the Filtering and Post Processing stage in the diagram where an offset can be added to the DTS reading to correct for any variation in the digital sensors.

To me it makes no sense that Intel would manufacture a batch of processors and then bin them based on what temp they should be able to run at.
"This one looks like it can run at 85C so we'll set Tjmax=85 and then the next one gets set to 87 or 90 or ....."

It makes a lot more sense that Intel determines for long term reliability and for stability that the first generation of C2D processors can run fine at up to 85C so they set that value to every processor to avoid excessive warranty claims. With further testing and with improved manufacturing they feel that their second generation of processors built on the Allendale core can run reliably up to 100C so they bump Tjmax up 15C.

Whether my interpretation or yours is right isn't too important. CoreTemp 0.95 tells you the DTS reading directly and references that to either 85C or 100C depending on your processor. It then calculates a core temperature based on one of those two reference points.

My processing power first gets reduced when DTS=2. If you're not overclocked then you should be able to continue and get to DTS=0 without any loss in stability. When fully overclocked, I found that the length of time that Orthos could run without any errors decreased when DTS dropped below about 13. That's the important number for my computer. I have great long term stability at DTS=15 and not so great when DTS=10.

Thanks for that article. Every little bit of information helps.

[fgw]

Originally Posted by unclewebb

Is there any documentation from Intel or any evidence from other users to support that? I'm not saying it's not true. I'm just interested like everyone else in what's really going on.

joebuffalo, might have referenced the following paragraph in the Thermal and Mechanical Design Guidelines to be found here:
http://www.intel.com/design/processo...nex/313685.htm

4.2.8 THERMTRIP# Signal

The temperature where the THERMTRIP# signal goes active is individually calibrated during manufacturing. The temperature where THERMTRIP# goes active is roughly parallel to the thermal profile and greater than the PROCHOT# activation temperature. Once configured, the temperature at
which the THERMTRIP# signal is asserted is neither re-configurable nor accessible to the system.

i would interpret this in the same way. individually calibrated during manufacturing let me assume this temperature is different from one processor to the other.

also i have read, but unfortunately don't remember where: "this thermtrip value is calibrated during manufacturing on a per chip basis by burning some shunts on the processor and may vary from die to die."

another interesting read on this issue is the thread on the intel software network forum:
http://softwarecommunity.intel.com/i.../30222546.aspx

look at the post before the last one:
...Note Tj is not a fixed value and the IA32_TEMPERATURE_TARGET[15:8] value can vary from part to part. Tj is also not software readable....

...Some steppings of the mobile Intel® Core™2 processor do indicate Tj to be approximately 85 or 100 via a single bit in the EXT_CONFIG register (msr 0EEh) but desktop, workstation and server processors do not....

[fgw]

Originally Posted by unclewebb

ted3: Sorry man, thats not throttling.

When I brought my E6400 up to 85C it was definitely throttling. On the Intel C2D there are two types of throttling.

http://www.intel.com/design/processo...als/253668.pdf
Here's a quote from page 13-5 of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Vol. 3A:

"One mode modulates the clock duty cycle; the second mode changes the processor’s frequency. Both modes are used to control the core temperature of the processor."

When a C2D processor first starts to approach Tmax the duty cycle will be reduced from 100% to 87.5%, 75% and continuing down to 12.5% in 12.5% increments. If the temperature of the processor still can't be controlled then the second mode kicks in which reduces the processor frequency (MHz) like you experienced. The first "duty cycle" throttling happens approximately 3C or 4C before Tmax.

this two modes (thermal monitor and thermal monitor 2) are not kicking in in sequence. you can select in bios, or trough software by writing to some registers, which thermal monitor mode you want to use. both start at the same temperature at prochot#.
and yes, thermal monitor 2 is the more powerful one as not only fsb but also vcore gets reduced.

[unclewebb]

Thanks fgw & joebuffalo for the additional info. Looks like I got some more reading to do!

[joebuffalo]

It certainly looks like Tj_max is higher on the L2's...do we agree on this?

So my new question: Is it *wise* to run yourn e4300 at the same DTS as an e6600? Just because the Tj_max was raised, does that mean we *should* be running our L2 processors at a higher absolute temperature? Obviously we can...but should we?

[fgw]

Originally Posted by joebuffalo

It certainly looks like Tj_max is higher on the L2's...do we agree on this?

So my new question: Is it *wise* to run yourn e4300 at the same DTS as an e6600? Just because the Tj_max was raised, does that mean we *should* be running our L2 processors at a higher absolute temperature? Obviously we can...but should we?

i would say it's always good to keep temps as low as possible. besides that i would not hesitate to increase vcore, and temps obviously too, until dts approaches 0c. intel would not have changed this tjmax if reliability cant be maintained at this temps.
anyway, to keep some safety margin would be a good idea for sure. i personally would keep this margin in a range of 10c to 15c.
as vcore is increased, temps need to be decreased in order to keep electromigration and thus reliability under control. so i would add another 20c to this safety margin.
for coretemp, this leads to a dts reading of about 35c or

• a temp reading of about 50c if your tjunction in coretemp is 85c and to
• a temp reading of about 65c if your tjunction in coretemp is 100c.

i know there is some talks about this issue (electromigration) going on in various threads so i wont comment on that right now. found some documents explaining this and will start a thread on this later on.