4x4 Quadfather = quad core MCP x 2!!!

[vitaminc]

http://www.theinquirer.net/default.aspx?article=35333

AMD follows Intel with Quadfather One

The die is cast

By Theo Valich: Thursday 26 October 2006, 08:28
WE MANAGED TO learn the official NDA expiry date and the launch of AMD's quad core offering. Or, should we say, its dual die dual socket chip.

After AMD laughed off Intel's dual core and upcoming quad core microprocessors as "not true multicore", with the main reason they physically share two dies, it seems to have done the same thing. Intel's Pentium D "Presler" consisted of two Cedar Mill cores, Core 2 Extreme "Kentsfield" features two Conroe cores and shared the front side bus.

Quadfather or the 4x4 as AMD marketeers have it, is actually a dual die quad core chip, using the Opteron processor socket and will launch on November 14th. The nForce 680a, the launch chipset is proof that the AMD-Nvidia strategic alliance still has four legs.

The launch line up was revealed here, but the pricing has been "re-constructed" severely downwards, with the fastest CPU pack now matching the price of Intel's Kentsfield. µ

Now Quadfather 4x4 should outperform Kentsfield :o 8 cores vs 4 cores!!!

[perkam]

http://www.theinquirer.net/default.aspx?article=35333


Now Quadfather 4x4 should outperform Kentsfield :o 8 cores vs 4 cores!!!

8 cores ??? It's 4 cores vs 4 cores...it must be the trashed deerhound server proc that AMD scrapped to make way for K8L. (Basically two Rev F/Rev G cores on one die)

That's going to be some crappy proc...

Perkam

[gillll]

"with the fastest CPU pack now matching the price of Intel's Kentsfield. µ "


i do hope !

please don't let me buy an intel!!!

[cky2k6]

if this is true, octa core for less than 1 kentsfield!

[Syn.]

it dosnt make sence. QuadFather is when they put 2 duel core prorecessors on the same motherboard which has 2 socketts. INQ is saying that its actually now two chips put on the same die. I am sorry but wtf?

After INQ said that DX9L was going to be released on XP i dont trust a single word they say. Can we please introduce a rule that all INQ stories are named "Rumor"?

[gillll]

yup no one give another 4 cores for free.

[Cooper]

You forgot that AMD soon will reveal quad-core SocketF CPUs which will work in any "quadfather" mobo with just a BIOS flash

[perkam]

meh...all this excitement over AMD finding more ways to keep demand for Rev F/RevG from dropping like a nail in water ahead of K8L production.

Most likely Quadfather will be done smithfield style with two dual core 90nm dies on one proc...as OEMs will eat up the little 65nm shipments AMD does send out by q4 2006/q1 2007.

Perkam

[vitaminc]

8 cores ??? It's 4 cores vs 4 cores...it must be the trashed deerhound server proc that AMD scrapped to make way for K8L. (Basically two Rev F/Rev G cores on one die)

That's going to be some crappy proc...

Perkam

both are quad core MCP, but 4x4 platform is for dual sockets. :p

Kents will still dominate single quad core MCP vs. MCP k8, but 4x4 sounds like 2 K8 QC MCP for the same price as a QX Extreme kents.

[gillll]

maybe this is the first step of mp where the cpu is hybrid cpu and gpu ?

the matrix of load balancing possabilities in this way is much larger then current systems

u'll have cores on 2 sockets and no "vga card"
all of the cores will load balance the system
whereas today the system has battleneck due to the cpu/gpu distance.

[onewingedangel]

All the inq were saying is that after trashing intel for having to scrape together a product, amd did exactly the same for 4x4. Its still 2 sockets each with a dual core processor. Intel went with dual die single package MCM to slap together a non native quad core system for enthusiasts, and amd went with dual die dual package, dual socket.

The inq were either deliberately ambiguous with the language to generate traffic, or didn't properly check their work.

[nn_step]

All the inq were saying is that after trashing intel for having to scrape together a product, amd did exactly the same for 4x4. Its still 2 sockets each with a dual core processor. Intel went with dual die single package MCM to slap together a non native quad core system for enthusiasts, and amd went with dual die dual package, dual socket.

The inq were either deliberately ambiguous with the language to generate traffic, or didn't properly check their work.

Basically AMD slammed Intel for MCM
and the INQ is Slamming AMD for 2P

[uOpt]

Hm...

I think it is not very likely to be true (that it is dual socket quad-core = 8 cores).

But I wouldn't be too surprised either. I remember just recently betting with somebody that AMD would do the dual-die trick, too. It just makes too much sense if you have heat under control - the simplifications for the motherboard are substancial. Of course I made that bet when I said they do 8-core chips by combining two 4-core dies but who knows - maybe they use QuadFather as a testbed.

If they give me an overclockable 8-cores I'd buy it no matter what.

[freecableguy]

*Ahem.* Hate to break up this party but I must...

AMD CPUs communicates with the SPP via an HyperTransport tunnel, same as the SPP communicates with the MCP (via an HT tunnel). Placing 2 (dual-core or otherwise) dies on a single package without changing the number of CPU package pins means more than just 4 cores in one package. It also means that each die can only receive 1/2 of the maximum BW available from the PCI-e buses attached to the SPP or MCP. Same number of pins, same bus speed, same data availability....one HT link.

If you thought Intel's "antiquated" FSB design was BW limited wait until you see this. Intel knew what they were doing. They knew all they had to do was scale the FSB to get more BW. AMD has to "overclock" the IMC (or design a new one) in order to increase BW. As you can see, each design has its pros and cons. AMD is about to experience the con.

Plus don't forget, the second CPU is going to be attached via an HT link to the first CPU (the SPP only allows for one HT link via the only set of pins available). This means that all the data throughput from the second CPU (and it's associated memory) as well as any video data must pass through the first CPU on their way to the PCI/PCI-e bus. *choke*

-FCG

[nn_step]

*Ahem.* Hate to break up this party but I must...

AMD CPUs communicates with the SPP via an HyperTransport tunnel, same as the SPP communicates with the MCP (via an HT tunnel). Placing 2 (dual-core or otherwise) dies on a single package without changing the number of CPU package pins means more than just 4 cores in one package. It also means that each die can only receive 1/2 of the maximum BW available from the PCI-e buses attached to the SPP or MCP. Same number of pins, same bus speed, same data availability....one HT link.

If you thought Intel's "antiquated" FSB design was BW limited wait until you see this. Intel knew what they were doing. They knew all they had to do was scale the FSB to get more BW. AMD has to "overclock" the IMC (or design a new one) in order to increase BW. As you can see, each design has its pros and cons. AMD is about to experience the con.

Plus don't forget, the second CPU is going to be attached via an HT link to the first CPU (the SPP only allows for one HT link via the only set of pins available). This means that all the data throughput from the second CPU (and it's associated memory) as well as any video data must pass through the first CPU on their way to the PCI/PCI-e bus. *choke*

-FCG

Each Proc would have half the bandwidth.
Which with DDR2-800
is about as much as dual channel DDR2-400 for each. Which honestly isn't horrible but it doesn't help much

[iddqd]

*Ahem.* Hate to break up this party but I must...

AMD CPUs communicates with the SPP via an HyperTransport tunnel, same as the SPP communicates with the MCP (via an HT tunnel). Placing 2 (dual-core or otherwise) dies on a single package without changing the number of CPU package pins means more than just 4 cores in one package. It also means that each die can only receive 1/2 of the maximum BW available from the PCI-e buses attached to the SPP or MCP. Same number of pins, same bus speed, same data availability....one HT link.

If you thought Intel's "antiquated" FSB design was BW limited wait until you see this. Intel knew what they were doing. They knew all they had to do was scale the FSB to get more BW. AMD has to "overclock" the IMC (or design a new one) in order to increase BW. As you can see, each design has its pros and cons. AMD is about to experience the con.

Plus don't forget, the second CPU is going to be attached via an HT link to the first CPU (the SPP only allows for one HT link via the only set of pins available). This means that all the data throughput from the second CPU (and it's associated memory) as well as any video data must pass through the first CPU on their way to the PCI/PCI-e bus. *choke*

-FCG

Isn't overclock and scale essentially the same thing? Intel has to overclock their FSB, AMD has to scale their HTT bus. Meh.

(It is scalable!)

[perkam]

Welcome to XS....



Perkam

[arisythila]

Lol

[3NZ0]

Welcome to XS....



Perkam

Actually laughed out loud

[grimREEFER]

2 cloverton's is better

[Gag3]

2 cloverton's is better

Welcome to XS....



Perkam

Intel Fanboy Alert.

[perkam]

Intel Fanboy Alert.

I don't know if you can say that about grimreefer...I don't think anyone with a smithfield in their sig can possibly be an Intel fanboy

Perkam

[Charles Wirth]

Plus don't forget, the second CPU is going to be attached via an HT link to the first CPU (the SPP only allows for one HT link via the only set of pins available). This means that all the data throughput from the second CPU (and it's associated memory) as well as any video data must pass through the first CPU on their way to the PCI/PCI-e bus. *choke*

Very true, FCG please show a block diagram

[nn_step]

Here is how I see what AMD would do, should they Choose MCM

[freecableguy]

Very true, FCG please show a block diagram