**Unified** DFI LanParty UT 790FX-M2R-M2RS / Phenom /Data Base Thread**

[Rammsteiner]

I'm looking at 3 options. Get a better Air sink, I've though of water but it's a maintenance issue and a pain.
Leave it at Stock until we get more results or can resolve the issue but continue to experiment on occasion.
Put the 5600 back in and use the Kentsfield for quad work.

Better cooling is always a good thing of course. Get a TRUE or so, very easy to install as well.

For your 2nd option, doing the same here with a little testing now and then. But Im mainly waiting for SB750. If it turns out my chip is still crap anyway Ill order a new chip as well. I guess in one or even two months steppings etc are already quite a bit better.

Option 3, could do. But might as well keep your Phenom in and still use your Kentsfield for the quadwork.

Im looking to watercool my stuff though. I know it's crap for maintenance, but well. Ill buy most waterblocks from the same manufacturer to decrease the chance that materials are going to react with each other. Also getting a Danger Den fillport to be able to quickly add some coolant as maintenance part. And the refilling, well, so be it lol.

[Brother Esau]

Currently ~ Testing ~ 5/5/2008 "Beta" Bios will post up some stuff when available

[justapost]

0x2e is SPD EEPROM on mine.
Mine seem to be similar with a few differences but I'm on SB600 not SB700 and 770 chipset. HIH

Nope the SPD EEPROMS are at 0x50 and 0x51. Your sensor chip has an smbus interface at 0x2e but was also found on the isa bus.
0x38 seems to be the SB interface on all 7xx chipsets. I have this on all boards.
0x69 is the clockgenerator you can dump him with "i2cdump 0 0x69 s".

[justapost]

If you want to change your cpu multis individual and don't want to use AOD you can use this method.

1. Set "Cool'n'Quiet" to Auto (bad sideffect you can not use a
   nb multi beside stock (9x or 10x) with newer bios versions.
2. Boot into windows make sure you have the phenom drivers from amd installed on winxp
3. Under windows open the Energy Options Dialog and switch to the mode for lowest battery usage.
4. Start AMD Power Monitor and CrystalCPU's MSR Editor.
   
   This is how it looks here with an 9600BE
   
   
5. Select a core In CrystalCPU's main window and read register 0xc0010064 in the MSR Editor. This is the register for the normal power state (p-state-0) at 0xc0010065 is the register for the energy saving power state (p-state-1). If you select "lowest battery usage" in the energy options dialog your cpu will run in p-state-1 in "Desktop" mode it's p-state-0.
6. The last digit is responsible for the cpu-multi.
   
   The frequency is 1600MHz+digi*100MHz, so in my case 1600MHz+700MHz=2300MHz.
   
   Change it to your desired value and hit WRMSR. In my screenshots I choose core0 and 8 as the last digit means 2400MHz for core0.
7. In the Energy Options Dialog switch into "Desktop" mode. The cpu
   will now use the new settings you defined in the p-state-0 register.
   
   

Beside the cpu multi you can also define CPU-VID,NB-VID, CPU-DID and NB-DID here. Look at page #24 of the "Official" DFI thread for further information.

[KTE]

Nope the SPD EEPROMS are at 0x50 and 0x51. Your sensor chip has an smbus interface at 0x2e but was also found on the isa bus.

That would be logical, but are you sure? The device at 0x2e crashing your system can only be the hardware monitoring I/O chip then.

0x38 seems to be the SB interface on all 7xx chipsets. I have this on all boards.
0x69 is the clockgenerator you can dump him with "i2cdump 0 0x69 s".

Thanks, will check it out later. I'm off it now, wish they made AOD or something similar for it so I could quickly test stability in Linux

[Brother Esau]

Anyone have any thoughts on this new beta release?

[Rammsteiner]

Justapost, again, thx a very lot for that!

Though i noticed just one little strange thing:

I played with Core 4 in CCPUID and set it to 2.9Ghz. But I ran Prime and it rebooted. Well, I restart and set 2.8Ghz again on the 4th core. But AMD Power Monitor now reads the 2nd core to be 2.8Ghz, so does CPU-Z. However, the 4th worker thread in Prime95 was running the fastest of all of them.

So exactly what core got the OC now? the 2nd (Core #1) or the 4th (Core #3)?

[EDIT] Well, Central Brain Identifier shows the 4th core to be OC'd as well lol...

[justapost]

I finaly managed to cripple the bios on the board with an k8 cpu.

I ran a few tests on 0x2e whom ran fine. Next lm-sensors version should have an updated detection routine to sort out the dangerous chip at 0x2e.

Then i tried "i2cdetect 0" which did not show the clock generator chip at 0x69 now with the k8. I was curious if i can dump the chip and tan "i2cdump 0 0x69". I got only XX's as response. I tried "i2cdetect 0" again and now even the chip at 0x2e was gone. I thought, k the smbus interface does no longer work coreect so i tried to reboot. Since then the borad stucks at C1 no mather what cpu i put in.
The M3A works fine with the 5000BE i used for the latest test on the Sapphire.

till i get the board boot proper again.

Justapost, again, thx a very lot for that!

Though i noticed just one little strange thing:

I played with Core 4 in CCPUID and set it to 2.9Ghz. But I ran Prime and it rebooted. Well, I restart and set 2.8Ghz again on the 4th core. But AMD Power Monitor now reads the 2nd core to be 2.8Ghz, so does CPU-Z. However, the 4th worker thread in Prime95 was running the fastest of all of them.

So exactly what core got the OC now? the 2nd (Core #1) or the 4th (Core #3)?

[EDIT] Well, Central Brain Identifier shows the 4th core to be OC'd as well lol...

That is really odd. I'd expect at least AMD Power Monitor and CBId to read from the core's msr registers.
Can it be that there are two ways to bind a task to an core. One uses the msr registers numbering and another one uses windows internal numbering (whom seems to change during reboots).

[Rammsteiner]

Ive no clue. The last three attempts the results stayed the same though, but not like the 1st time. But still it's strange two programs report Core x to be OC'd and two programs report Core y to be OC'd... Like lol wtf confusion.

Still I dont know what I was thinking. This MSR stuff is nice but now I think about it, if my board sucks that bad OC'ing single cores wont change results?

Ill try a little bit more. I ran a 16h+ Prime Blend with WinAmp playing music with 4th core on 2.8Ghz stock Volts. 2.9Ghz wasnt loved much though, and at least core 1 and 2 didnt want to run 2.9Ghz either with the 4th at 2.8Ghz. Both time I froze... At least better than the Machine Check Exception BSOD though.

But I didnt play with Voltage options yet, maybe it's just a lack of Vcore. Or, most likely, Ive a bad chip anyway. After all Tony managed insane results on both his DQ6 and M2R, and Brother managed to get 2.8Ghz at low Vcore.

Ill of course test some more, already have the MSR field number for P0 in my head lol. And whenever my exams are over and have some money to waste Ill get SB750 and another chip.

[KTE]

Then i tried "i2cdetect 0" which did not show the clock generator chip at 0x69 now with the k8. I was curious if i can dump the chip and tan "i2cdump 0 0x69". I got only XX's as response. I tried "i2cdetect 0" again and now even the chip at 0x2e was gone. I thought, k the smbus interface does no longer work coreect so i tried to reboot. Since then the borad stucks at C1 no mather what cpu i put in.

Like I said in other post, the app can cause the system to go haywire. Was that first time you tried to get the dump?

That is really odd. I'd expect at least AMD Power Monitor and CBId to read from the core's msr registers.

This is what I mentioned a few days back. On different boots, different reads. Some apps get them from the same registers though
I've seen their debug dumps, you can ask VVJ.

Can it be that there are two ways to bind a task to an core. One uses the msr registers numbering and another one uses windows internal numbering (whom seems to change during reboots).

AOD, CPUZ, CBID, AMDPM, CCPUID label cores differently. Sometimes one core is another in the other app, thats what I said hindered me trying to oc individual cores. Each time you reboot, core arrangement might very well be different

For me, I change it until AMD PWM and CCPUID read similar. Thats worked fine so far...

ATM, my highest stable is 1.38v 3000/3000/2700/2800 with that method.

[KTE]

BTW, just to add: I've seen Rammsteiner's register dumps of MSR C001 0064, his core registers in P-State 0 are not changing multiplier at all even when his system tells him he's running overclocked.

So even when CPUZ shows: 1.3VID 200x13.5 2700
MSR P0 shows: 0x28002809 aka 1.3VID 12.5x multi

Had no idea what thats about, but a little experimentation showed me MSR C001 0070 is changed instead and the MSR C001 0064 just stays default in his case.

Ramm, many PMs, all were lost half way through system crashes, so I'm waiting to get it stable before trying again, sorry

I hate taking time on PMs and then you lose it

[justapost]

Like I said in other post, the app can cause the system to go haywire. Was that first time you tried to get the dump?

With the Phenom there was a chip at 0x69 whom I dumped many times. I expected it to be the clock generator. I only have the specs for an similar clock generator and I was not yet able to figure it's registers out. I focuesd on the M2A-VM clock generator yesterday, because i have the specs of that clockgen chip and it is the simplest one.

With the k8 cpu there was no chip at 0x69 according to i2cdetect 0. I was curious if that chip was just not detected and tried to dump that address 'i2cdump 0 0x69". It was not the first time i tried to dump an nonexistent address and the result was the same as with other nonexistend address dumps. Just XX's and no hex values.
However after that test "i2cdetect 0" did no longer show the 0x2e chip and since then i can not get beyond C1.

This is what I mentioned a few days back. On different boots, different reads. Some apps get them from the same registers though
I've seen their debug dumps, you can ask VVJ.

AOD, CPUZ, CBID, AMDPM, CCPUID label cores differently. Sometimes one core is another in the other app, thats what I said hindered me trying to oc individual cores. Each time you reboot, core arrangement might very well be different

For me, I change it until AMD PWM and CCPUID read similar. Thats worked fine so far...

I saw your postings few days ago. Most astonishing to me is that AMD PM uses different labels than the MSR-Registers. I thought it completely relies on those registers. M$ developers should shed some light how they bind threads to cores.

[Rammsteiner]

BTW, just to add: I've seen Rammsteiner's register dumps of MSR C001 0064, his core registers in P-State 0 are not changing multiplier at all even when his system tells him he's running overclocked.

So even when CPUZ shows: 1.3VID 200x13.5 2700
MSR P0 shows: 0x28002809 aka 1.3VID 12.5x multi

Had no idea what thats about, but a little experimentation showed me MSR C001 0070 is changed instead and the MSR C001 0064 just stays default in his case.

Ramm, many PMs, all were lost half way through system crashes, so I'm waiting to get it stable before trying again, sorry

I hate taking time on PMs and then you lose it

But I was running 12.5 multi. Did I say I was running 13.5 multi then? If so, sorry, Im running 12.5.

And KTE, we've the same stepping right. I might add a little Vcore or something then. I just looked at the Phenom stepping/OC thread and it looks like all stepping starting with the 'B' at least do better already. Mine starts with 'A', maybe that's the whole crap thing about.

[Rammsteiner]

For me, I change it until AMD PWM and CCPUID read similar. Thats worked fine so far...

ATM, my highest stable is 1.38v 3000/3000/2700/2800 with that method.

Do you mean that when APM and CCPUID read the same speeds, no matter what core number? Like before you had Core #3 on both CCPUID and APM OC'd, reboot and now they both say Core #1, this way it's still correct?

Or if they read Core #1 you change your OC back to default and just try out a different CPU to OC with MSR and continue this untill they both say Core #3 again?

If so, this would mean we've NO clue what core we're actually OC'ing lol. It doesnt matter as long as we're sure we're testing the same core as we tested before though.

If I would have known this earlier I would have written the core # I had with the 2.8Ghz OC

[KTE]

With the Phenom there was a chip at 0x69 whom I dumped many times. I expected it to be the clock generator. I only have the specs for an similar clock generator and I was not yet able to figure it's registers out. I focuesd on the M2A-VM clock generator yesterday, because i have the specs of that clockgen chip and it is the simplest one.

With the k8 cpu there was no chip at 0x69 according to i2cdetect 0. I was curious if that chip was just not detected and tried to dump that address 'i2cdump 0 0x69". It was not the first time i tried to dump an nonexistent address and the result was the same as with other nonexistend address dumps. Just XX's and no hex values.
However after that test "i2cdetect 0" did no longer show the 0x2e chip and since then i can not get beyond C1.

Sad news damn

Most astonishing to me is that AMD PM uses different labels than the MSR-Registers. I thought it completely relies on those registers. M$ developers should shed some light how they bind threads to cores.

I have no idea how they're set

I would love to know how though.

Presumably, I'm thinking, CCPUID/CPUZ/CBID do not change core numbering but AOD/AMD PWM do. I suspect thats what causes the confusion.

But I was running 12.5 multi. Did I say I was running 13.5 multi then? If so, sorry, Im running 12.5.

Yeah it said you were running:

"Voltages were stock, so were VID's. I only changed multi's, first time I did Core #0 14x and the other 3 cores 13x."

Did I misunderstand that?

And KTE, we've the same stepping right. I might add a little Vcore or something then. I just looked at the Phenom stepping/OC thread and it looks like all stepping starting with the 'B' at least do better already. Mine starts with 'A', maybe that's the whole crap thing about.

My reply would've mentioned, that don't look at steppings

Do you mean that when APM and CCPUID read the same speeds, no matter what core number? Like before you had Core #3 on both CCPUID and APM OC'd, reboot and now they both say Core #1, this way it's still correct?

Or if they read Core #1 you change your OC back to default and just try out a different CPU to OC with MSR and continue this untill they both say Core #3 again?

Core0/1 on mine stay put, core2/3 interchange randomly. I can find out by using multiple apps though, tedious procedure.

[justapost]

Sad news damn

Good news, the board is back.

I tried tony's reverse battery method. I left the totaly unplugged board with the clear cmos jumper set and the batter mounted revers alone fopr a few hours and now it's working again. Glad I had luck this time.

[Rammsteiner]

Glad to hear that justapost.

Anyway, was running 3h+ stable, was typing a post here and everything went black and board not responding to reset/power buttons once again. Had to use PSU...

Either Ive a crap chip or my board is really totally borked.

I'd like to believe it's my board, but in the end some people hit 3Ghz with stock Volts. Whether it's 100% stable (ie idle stable), I dont know. But at least their Phenom saw 3Ghz+ in Windows, mine hardly saw 2.9Ghz at any Vcore. Maybe a combination.

So once again, MSR OC'ing didnt bring me anything new. Ill still have to wait for SB750 and/or another Phenom. Oh well, the CPU at stock is fast enough to play Eve-Online so Im fine for a while. Though I really hope to get something started in a month or so.

[xKraMx]

Has anyone had a issue trying to get this board to cold boot?

So far ive tried two different boards and two different power supplies and after the first boot if i shut it down and try to cold boot again leds/fans will spin for a second then nothing well happen. In order to get it to boot up again I have to remove power from the motherboard by flipping the switch on the psu then after any leds on the motherboard are out it will boot or atleast attempt to boot again.

edit: (just incase my sig didnt show for some reason)
DFI LanParty UT 790FX-M2R
Thermaltake Toughpower W0133RU 1200W

[stocius]

Has anyone had a issue trying to get this board to cold boot?

So far ive tried two different boards and two different power supplies and after the first boot if i shut it down and try to cold boot again leds/fans will spin for a second then nothing well happen. In order to get it to boot up again I have to remove power from the motherboard by flipping the switch on the psu then after any leds on the motherboard are out it will boot or atleast attempt to boot again.

Nope, I'm on air. But I'm looking into cold atm so if you find anything please let me know, thanks.

[Tony]

Has anyone had a issue trying to get this board to cold boot?

So far ive tried two different boards and two different power supplies and after the first boot if i shut it down and try to cold boot again leds/fans will spin for a second then nothing well happen. In order to get it to boot up again I have to remove power from the motherboard by flipping the switch on the psu then after any leds on the motherboard are out it will boot or atleast attempt to boot again.

edit: (just incase my sig didnt show for some reason)
DFI LanParty UT 790FX-M2R
Thermaltake Toughpower W0133RU 1200W

Try just pushing reset, my boards here hang but boot no issues if I just push the reset button

[justapost]

Glad to hear that justapost.

Thanks, after I got the board working i did a few other tests jean from the lm-seonsors list recommended.

In short at 0x2e lives a chip whom is responsible for vdimm. I can read out that chip with modified i2c-tools.
>i2cget 0 0x2e
0x35
Normaly you can readout an specific register of an chip like this
>i2cget 0 0x2e 0x01
That returns the value of register 0x01 from the chip at 0x2e. Now that chip at 0x2e behaves different. The chip has only one register and
>i2cget 0 0x2e 0x01
results in 0x01 been written into the chips only register and the value is returned. This would mean ~3.2V vdimm.


I figured it out because my system froze as i tried to write 0x32 in that register. After that I had C1's till i removed a dimm. That dimm did not work in the Sapphire board for a while. After i tested it in the gbt board it works again in the sapphire now.
So after i got the board working i measured vdimm with different values in the 0x2e register

0x34 => 1,971V
0x35 => 1,942V
0x36 => 1,916V
0x37 => 1,892V

If an application probes this chip by trying to read address 0x00 the normal way it will result in the highest possible vdimm.

Sidenote: The chip at 0x4c is the cpu's thermal sensor interface. At address 0x01 the core temp can be read out.

Anyway, was running 3h+ stable, was typing a post here and everything went black and board not responding to reset/power buttons once again. Had to use PSU...

Either Ive a crap chip or my board is really totally borked.

I'd like to believe it's my board, but in the end some people hit 3Ghz with stock Volts. Whether it's 100% stable (ie idle stable), I dont know. But at least their Phenom saw 3Ghz+ in Windows, mine hardly saw 2.9Ghz at any Vcore. Maybe a combination.

So once again, MSR OC'ing didnt bring me anything new. Ill still have to wait for SB750 and/or another Phenom. Oh well, the CPU at stock is fast enough to play Eve-Online so Im fine for a while. Though I really hope to get something started in a month or so.

If it helps my 9600BE is not prime95 stable at stock 2.3/1.8GHz 1.25/1.25V.

[KTE]

^

Now or has it never been?

Thanks for the info, dangerous

[justapost]

^

Now or has it never been?

Good question i never ran it at stock before, always at 2.6GHz. Since I mounted the chip i always ran stock or lower frequencies at 1.25V. For my sensor testing i allways used the 500BE for the 0x2e register.

Thanks for the info, dangerous

Indeed i wonder what types of probing everset sandra and so on uses.

[Rammsteiner]

Well, that sucks even more justapost.

On the otherhand, Ive no clue if my chip is stable at stock. I ran Prime when I just got it for 10 hours. But we all know Phenom+Prime=useless. And in the end at stock I enever searched for instability, but maybe if I would leave it for two weeks on I would crash... But I never leave my PC on for that long. And I dont feel like trying out either.

Im done for a while, now enjoying the PC. My 2nd HD3870 is on repair tour, if I get it back Ill Vmod that one and try 900+/1300+ in CF mode. DQ6 and 6400+BE are on RMA as well.

Maybe I should get like a 500W PSU, a very cheap GPU (like HD3400), a cheap HDD and use DQ6 for purely testing new Phenoms without having to screw around in this PC all the time

[seeker010]

how come new bios don't allow nb fid/did change when enabling cool'n'quiet?