AMD's Bobcat and Bulldozer

[blindbox]

I hope they'll talk about platforms (both server and desktop) on the second wave of slides.

[informal]

Another deck of slides,or a good part of them, is up at certain (well) known website that deals with hardware inner things . I don't want to say which one since the NDA is not over yet(1hour remaining) so there is a chance it gets pulled . If you understood my word play you will know which website it is .

edit:
since terrace asked me on SA forum about the load/store BW here it is,confirmed(2x128bit L and 1x128bit S capability,per core-the slide talks about dedicated integer cores and distinct/non shared features).This is from the other slide deck with more detailed info on Bulldozer.The thing i noticed about the shared FPU is the dual 128bit packed integer pipelines ,along the 2 128bit FMACs that sit inside the FPU monster.

[xlink]

Single-thread performance --> low-thread performance, due to the nature of 2-cored modules and Intel's 2-way HT.

So you are essentially saying "wtf cares about 4-threaded performance?!?!"

Well, that encompasses the vast majority of what you'll be doing on the desktop most of the time, so, the answer is: most people.

sc2 only uses 2 cores. Photoshop is limited by the user's skill not the computer. Web browsers are dependent upon the connection

so the answer is: only nerds who rage over 1/10th of a frame rate on forums.

desktops are single thread oriented

[MrMojoZ]

So this is AMD's Hot Chips presentation? Gosh, they didn't say anything new except for Bobcat's L1 and L2 cache sizes as Hans has already said...

Saw AMD in thread title and couldn't resist huh? Try harder.

[terrace215]

desktops are single thread oriented

And um, that's the problem for BD.

[informal]

And um, that's the problem for BD.

Why do you say that ?
How do you know how it performs in underutilized scenarios?

[terrace215]

Well, that doesn't actually go as far as saying you can do all 3 (2 loads, 1 store) at the same time...

There's now info up at tech report, too.

[informal]

Well, that doesn't actually go as far as saying you can do all 3 (2 loads, 1 store) at the same time...

Well that's the most granular bit you will get for now . You can interpret it as you wish

[Hans de Vries]

And um, that's the problem for BD.

1) JF told you at the other thread that IPC is higher.

2) If that's true then the higher frequency design comes on top of that.

3) And last but not least: Power gating Turbo now allows much higher single core frequencies.


Looks like a 1-2-3 speed bump for single thread performance to me....


Regards, Hans

[xlink]

1) JF told you at the other thread that IPC is higher.

2) If that's true then the higher frequency design comes on top of that.

3) And last but not least: Power gating Turbo now allows much higher single core frequencies.


Looks like a 1-2-3 speed bump for single thread performance to me....


Regards, Hans

fewer execution units...

those three factors coupled with other architectural improvements would need to be able to be at least 50% faster in some instances.

[slaveondope]

Its AMD, you got to have faith they'll give Intel something to think about

I love the under dog

[safan80]

I like how amd is combating HT by intel. I'm looking forward to both bobcat and bulldozer. Although I still wonder how AMD is going to complete in the mobile market against intel's atom.

[rcofell]

synthesizers do not floorplan. generally modern logic blocks are 50-100K gates, probably around 300-600K transistors. this is a rather large chunk when the core itself, including L1 & L2 it is probably <20M transistors.

Not exactly sure which context your mean when you say they "do not floorplan", but they definitely allow floorplanning at some level. The first step of synthesis, RTL -> Netlist, doesn't floorplan (it just cares about standard cells usage & timing estimates/constraints), if that's what you're trying to get at. However, the second step of synthesis, Netlist -> Placement (placement tool), definitely does floor-planning.

Tools like Cadence Encounter take floorplan constraints and allow for partitioning sub-modules, however like the picture above shows the results tend to look like a jumbled mess, since strict boundaries aren't adhered to.

Finally, chips from AMD has always been nicely ordered, pointing at a mostly hand made layout. I can imagine that it leads to an uneven power usage and unnecessary long circuits and timings. And wastes die space.

Well, historically [x86] chips from both camps have always been mainly custom layout in the datapath with a varying amount of synthesized control logic, seeing pictures like this is a bit of an eye opener from the norm

Another example is Intel's Pine-Trail (bigger):

The huge purple blotch running down the middle is all synthesized logic

AMD says (http://www.youtube.com/watch?v=VIs1CxuUrpc)
"Synthesizable with small number of custom arrays"
Together with what was said before I think one of the main goals that AMD wants to achieve is to have easily customizable processors. Add a gpu core here, some cache there and another core here. From the slide it looks like lots of their process is already capable of being laid out by a computer.
We have the caches, the integer units and the floating point units being the fixed hand optimized blocks with stuff like the x86 decode organically filling up the space in between. AMD also says it makes it easier to put the whole thing on a different process.

I've only limited knowledge about modern synthesizing and floor planning from working with some FPGAs.
Maybe Hans or somebody in the industry can say something about Bobcat?

You pretty much sum up my thoughts on the matter, it looks like they shot for a semi-custom approach by supplying some of the main datapath logic (not necessarily say the whole FPU, etc., just the important chunks) and the arrays as hard-macros/external-IP (in- or out-of-house, doesn't matter) while synthesizing the rest.

While they're definitely not unique in the approach, it will certainly provide a quicker process adaptation, since only a standard cell library and select logic/array-IP pieces would technically be necessary. Granted there's still a bit more work than just swapping libraries/IP and pressing a few buttons

lol, it is the exact opposite. hand layout is much better. humans are better at finding eulerian paths and coming up with clever layouts. computers cant really do that with all of the design rules and other parameters as effectively. the difference in performance is 2.6-7x faster with custom designed circuits.

really what happens is a coder will simulate his module and make sure it reaches the targeted timing, which is usually much higher than actual delay to assure robust operation. if the logic cant reach the speed it is either rewritten or circuit designers optimize it. in certain logic families it must be entirely custom designed.

circuits that are custom designed are usually things like power gating, clock distribution, and analog circuits such as pll's, dll's, and memory controllers/ io pads.

Just pointing out that while we humans can definitely be more adapt at coming up with these clever (sometimes novel) solutions to optimizing layout area/timing/congestion-constraints, it's also a significant capital and time investment, so it's for ROI and time to market reasons that it doesn't always work out. The case of Bobcat is obvious an example of this, and Atom for that matter.

Honestly I would find the logically optimal euler path to be much easier for a computer to solve
But yes computerized tools aren't very good when it comes to balancing the plethora of added constraints in a physical world, hence us restricting them to sub-optimal standard cells + wiring constraints.

[terrace215]

1) JF told you at the other thread that IPC is higher.

2) If that's true then the higher frequency design comes on top of that.

3) And last but not least: Power gating Turbo now allows much higher single core frequencies.


Looks like a 1-2-3 speed bump for single thread performance to me....


Regards, Hans

Hans, I wouldn't put much faith in "much higher single core frequencies", relative to phenom II.

As for the IPC, I could believe it is higher, but having seen how they've trimmed the cores in certain ways, not that much higher.

[crazydiamond]

Why do you say that ?
How do you know how it performs in underutilized scenarios?

they dont, but standard procedures say to enter amd thread and say anything negative about amd even if there is no proof to back it

[Chumbucket843]

they dont, but standard procedures say to enter amd thread and say anything negative about amd even if there is no proof to back it

you say that so much and i think it's easier to just either visit another forum, not get so upset, ignore the posts, or even just set certain users to ignore. notice it's not a big deal to anyone else. the shintai era is over dude.

some people dont like amd and you'll just have to deal with it. personally i am more frustrated with them (amd) more than anything else. i have high standards, especially from big companies. and yes AMD is a big semiconductor company.

[Hans de Vries]

AMD says (http://www.youtube.com/watch?v=VIs1CxuUrpc)
"Synthesizable with small number of custom arrays"
Together with what was said before I think one of the main goals that AMD wants to achieve is to have easily customizable processors. Add a gpu core here, some cache there and another core here. From the slide it looks like lots of their process is already capable of being laid out by a computer.
We have the caches, the integer units and the floating point units being the fixed hand optimized blocks with stuff like the x86 decode organically filling up the space in between. AMD also says it makes it easier to put the whole thing on a different process.

I've only limited knowledge about modern synthesizing and floor planning from working with some FPGAs.
Maybe Hans or somebody in the industry can say something about Bobcat?

Another nice example is the 1.9W TDP 2GHz hardmacro version of the dual
core ARM cortex A9 in the TSMC 40G process (total size of only 6.7 mm2)

http://www.arm.com/products/CPUs/Cor...ard-Macro.html



Regards, Hans

[Mats]

Another nice example is the 1.9W TDP 2GHz hardmacro version of the dual
core ARM cortex A9 in the TSMC 40G process (total size of only 6.7 mm2)

What's the reason behind the odd die shape, do you know?

[redpriest]

Hans, I wouldn't put much faith in "much higher single core frequencies", relative to phenom II.

Why? Does this boil down to your special insight with regards to GF's 32nm process?

[terrace215]

Why? Does this boil down to your special insight with regards to GF's 32nm process?

Phenom II hits what, 3.8 on turbo? Yeah, I don't see BD turboing much past 4GHz, *especially* on that GF process. Power just starts to climb so fast with frequency at that point.

[rcofell]

What's the reason behind the odd die shape, do you know?

It's supposed to still be a rectangle, the discrepancy is the white "missing" area is for external-IP (L2 cache SRAM mainly, but chip-level interfacing too).

[Calmatory]

Hans, I wouldn't put much faith in "much higher single core frequencies", relative to phenom II.

As for the IPC, I could believe it is higher, but having seen how they've trimmed the cores in certain ways, not that much higher.

1. Deeper pipeline. -> Higher clocks.
2. 32 nm Gate Last HKMG SOI. -> Higher clocks.
3. Inclusive cache hierarchy. -> Higher IPC.

[Mats]

Why? Does this boil down to your special insight with regards to GF's 32nm process?

No, it's because Intel is raising their turbo clock with 66 MHz, from 3733 MHz in 45 nm i7 880, to 3800 MHz in 32 nm i7 2600.

If Intel can only raise it with 66 MHz, then AMD should only be able to raise it with less than that, right? It's fundamentally impossible that AMD can do ANYTHING better, according to some people.
Yet, they keep on posting and bashing in threads about things they hate.. I mean, what's the point?

Maybe I should join a Britney Spears forum and see what being negative in a forum is all about, because I honestly don't know.

[god_43]

1. Deeper pipeline. -> Higher clocks.
2. 32 nm Gate Last HKMG SOI. -> Higher clocks.
3. Inclusive cache hierarchy. -> Higher IPC.

lol a trifecta eh?


i guess stp matters still....well thanks for all who explained why they view it as important.

[god_43]

No, it's because Intel is raising their turbo clock with 66 MHz, from 3733 MHz in 45 nm i7 880, to 3800 MHz in 32 nm i7 2600.

If Intel can only raise it with 66 MHz, then AMD should only be able to raise it with less than that, right? It's fundamentally impossible that AMD can do ANYTHING better, according to some people.
Yet, they keep on posting and bashing in threads about things they hate.. I mean, what's the point?

Maybe I should join a Britney Spears forum and see what being negative in a forum is all about, because I honestly don't know.

why Britney spears? there's nothing wrong with Britney!.....LEAVE BRITNEY ALONE!!!


http://www.youtube.com/watch?v=kHmvkRoEowc