AMD's Bobcat and Bulldozer

[Dimitriman]

John is this true?

Tbh I don't see ANY reason why AMD can't release 3 module (6 core) Bulldozer units besides product portfolio choices.

Each module is independent and the design would permit this choice fairly easily i believe.
Plus there will always be 4 module chips with 1 defective module to disable

[superrugal]

Tbh I don't see ANY reason why AMD can't release 3 module (6 core) Bulldozer units besides product portfolio choices.

Each module is independent and the design would permit this choice fairly easily i believe.
Plus there will always be 4 module chips with 1 defective module to disable

I just wondering how can bulldozer perform such a low power within 8 cores.

Finally JF answer me.

http://www.amdzone.com/phpbb3/viewto...37878&start=50

[JF-AMD]

i think were all interested about the IPC difference between 2 threads per module and 1, not how much turbo can overclock it, but just how a thread by itself will act (it looks like we already know its going to have 2MB of L2 all to itself)

I actually have a meeting on this at lunch. It's actually a pretty cool discussion. However, don't expect a detailed discussion until much later.

I believe the next round of "20 questions" answers (some time next week) will tackle part of this. But there are some pretty cool SW things to consider.

That is all I can say.

[JF-AMD]

I just wondering how can bulldozer perform such a low power within 8 cores.

Finally JF answer me.

http://www.amdzone.com/phpbb3/viewto...37878&start=50

I answered your other thread.

For the rest of you, we hit that today with 4-6 core server parts and the 6-8 core parts fit in the same socket with the same power/thermals. You can do the math on that.

[Manicdan]

I actually have a meeting on this at lunch. It's actually a pretty cool discussion. However, don't expect a detailed discussion until much later.

I believe the next round of "20 questions" answers (some time next week) will tackle part of this. But there are some pretty cool SW things to consider.

That is all I can say.

when your waiter stands next to you at very odd times listening in on the convo, you will be wondering if its me.

[ajaidev]

when your waiter stands next to you at very odd times listening in on the convo, you will be wondering if its me.

Or you could plant a bug and then invite a few special pal's "like me" to listen in via the net... ya it would be diabolical

[Frontl1ne]

So do we have a definitive/official response as to whether or not Bulldozer will be compatible with current AM3 motherboards? This thread grows too fast for me to follow :p

[Manicdan]

Or you could plant a bug and then invite a few special pal's "like me" to listen in via the net... ya it would be diabolical

i own AMD stock, if this got out and hurt the price, i would feel bad

infact i think he should be packing some heat and scare off anyone suspicious looking

[JF-AMD]

when your waiter stands next to you at very odd times listening in on the convo, you will be wondering if its me.

I think the fact that there is a waiter in the conference room at AMD would be enough of a tip.

I don't think I have had more than 2 lunches in restaurants in the last 6 months, just a bit busy around here.

[gallag]

I would not give AMD a hard time for needing a new mobo, I would rather they design the cpu then the mobo to suite rather having design trade offs to accomadate the older mobo tech.

[Manicdan]

I think the fact that there is a waiter in the conference room at AMD would be enough of a tip

it worked, we know exactly where to plant the bug. now i just need an inside man, a tracking bug (maybe a baby monitor?), and a black suv with tinted windows parked in the grass just 20ft away from the room. sounds easy

[Manicdan]

I would not give AMD a hard time for needing a new mobo, I would rather they design the cpu then the mobo to suite rather having design trade offs to accomadate the older mobo tech.

would be nice to know what AM3+ will offer that is going to be a deal breaker

[Chumbucket843]

John is this true?

sure a low voltage chip can do that. at 3GHz? unlikely.

Read the AT article.It is the hardest thing to do indeed,but the way this machine is built allows it to go a bit further ahead of itself(with all the BP,data speculation,much improved out of order loads and stores capability etc). I guess the more in depth slides from HotCHips will shed more light on this subject later today.

no, i will not read that article. i dont need someone to tell me the sky is blue either.

the only way to increase alu utilization efficiently is through software. using hardware to improve this is generally inefficient. gpu's are a good example of this. it is harder to exploit data parallelism but the majority of transistors in gpu's are sram in register files/caches, and alu's. this is about as lean as you can get.

[terrace215]

16KB L1D (down from 64KB in K10.5), only 2 ALUs per integer core (down from 3 in K10.5), longer pipeline... compensated by some op fusion, better prefetching & branch prediction, but: pretty clear now that the single- (and therefore low-) threaded integer IPC is NOT going to make a huge jump from K10.5. I'm not sure it will match Nehalem, even- might be close. SB should be well in the clear.

[blindbox]

The only thing I'm wondering with regards to AM3/3+ compatibility of bulldozer, are there no slides regarding it? It seems like everything is word of mouth.

I was quick to believe what Opteron146 has quoted but now that I think of it, there aren't any official slides regarding platform yet. Not all infos are released yesterday (or today for those still in the 24th).

[geo]

. In many ways the architecture looks to be on-par with what Intel has done with Nehalem/Westmere. We finally have a wider front end, branch fusion, power gating/true turbo and more aggressive prefetching. Whether or not AMD can surpass Sandy Bridge’s performance really boils down to how many Bulldozer modules you get at what price. If 2 module (4-core) Bulldozer CPUs go up against dual-core Sandy Bridge things could get very interesting.

- Anandtech

with all the delays (late ?) 2011 Bulldozer and now this. BD is looking more and more like Microsoft Vista. hope i'm wrong.

[terrace215]

It's more interesting that they slimmed down the integer cores to 2 ALUs/2 AGUs.

This is a big change from the 3 ALUs/3 AGUs that AMD has used for K7/K8/K10.
Combine this with the four wide front end/decoder and it is clear that BS is a
throughput design optimized for server type workloads.

It looks like AMD concluded that it can't match Intel in single core performance
and it would always have to throw 2 cores at every Intel core. It sat down and
looked carefully at how much sharing and trimming it could do to make 2 of its
cores closer in area and power to 1 Intel Nehalem/SB core. The biggest moves
are sharing front end and FPU between cores and slimming down the integer
cores. This should keep AMD in the game in servers where it can put two 8 core
devices into an MCM and sell it against 8 core SB and 10 core Westmere-EX.
The loss of the third ALU/AGU in the BD's integer cores likely won't make a lot
of difference to commercial server workloads which have low ILP and high MLP.
The sharing of the FPUs probably won't hurt HPC performance much because
with 8 cores per die and 16 cores per package memory system limitations will
tend to dominate.

IMO where it becomes problematic is building client devices based on the BD
architecture. AMD will really have to ratchet up its CPU clock rates to more
than make up for the loss in IPC from the slimmed down integer cores.


http://aceshardware.freeforums.org/a...iew-t1042.html

[informal]

What are we looking at here terrace? An opinion from traditionally anti-AMD guy(Demone) who has no real perf. data at hand? What "losses in IPC" is he talking about?

[btarunr]

Here we have the reason. Integrated PCI-Express controller.

EDIT: Well obviously not, but that what techpowerup claims.

There's "L3 Cache and NB" and "Integrated Northbridge Controller".

The "NB" in "L3 Cache and NB" is the northbridge component found on AMD processors since K8. The "Northbridge Controller" is the IOMMU (what we're used to referring to as northbridge, such as AMD 790FX) integrated into the processor die.

[LesGrossman]

It's more interesting that they slimmed down the integer cores to 2 ALUs/2 AGUs.
It looks like AMD concluded that it can't match Intel in single core performance and it would always have to throw 2 cores at every Intel core.

That's like saying that with K8 AMD concluded that couldn't match the higher cpu clocks of netburst and that would always have to throw more instructions per clock at Intel MHZ's.

Crysis 2 will support 8 cores, good luck with the single thread performance thing.

[-Boris-]

16KB L1D (down from 64KB in K10.5), only 2 ALUs per integer core (down from 3 in K10.5), longer pipeline... compensated by some op fusion, better prefetching & branch prediction, but: pretty clear now that the single- (and therefore low-) threaded integer IPC is NOT going to make a huge jump from K10.5. I'm not sure it will match Nehalem, even- might be close. SB should be well in the clear.

Size of the cache isn't everything, now it might be quicker, 8-way or more? And the L1 takes a pretty large die area on all K7 derivatives so the space might be used more efficient now. And as they said, you could quite easily make up for the lower cache size.
The pipeline part might be something good, Athlon 64 has a longer pipeline than K7, and core 2 has a longer pipe than A64, and nehalem has an even longer one, only prescott has a longer pipe than Nehalem among X86 cores. Now they might have evened out the execution to be more streamlined, and these stages could be related to prefetch, thus increasing effiency.
And when it comes to pipes, Phenom II has 3 pipes, that means 3 ALU or 3 AGU. While Bulldozer has 4 pipes, which translates to 2 ALU and 2 AGU. That means that Bulldozer most likely will have quicker execution than Phenom II, and might even save die space at the same time.
So even without the branch prediction, prefetch and op fusion Bulldozer might be faster. Now consider the very aggresive prefetch, which translates to better use of available bandwidth, enhanced memory controller, dual 128 bit FPUs, and possibly higher clockspeeds.

Bulldozer might be an insane performer, we simply have to little knowledge to judge at this point.

[god_43]

honestly wtf cares about single thread performance? geez if ppl cared about it, they would not be buying dual-cores even. the whole nature of multiple cores is for multi-threading, anything else is fail!

[Oliverda]

http://www.techpowerup.com/129392/AM...hitecture.html

Another one



waaa waa

techpowerup fail


"At the chip-level, there's a large L3 cache, a northbridge that integrates the PCI-Express root complex, and an integrated memory controller. Since the northbridge is completely on the chip, the processor does not need to deal with the rest of the system with a HyperTransport link. It connects to the chipset (which is now relegated to a southbridge, much like Intel's Ibex Peak), using A-Link Express, which like DMI, is essentially a PCI-Express link. It is important to note that all modules and extra-modular components are present on the same piece of silicon die. Because of this design change, Bulldozer processors will come in totally new packages that are not backwards compatible with older AMD sockets such as AM3 or AM2(+). "




official slide from last year's Analyst Day:

[Opteron146]

The only thing I'm wondering with regards to AM3/3+ compatibility of bulldozer, are there no slides regarding it? It seems like everything is word of mouth.

I was quick to believe what Opteron146 has quoted but now that I think of it, there aren't any official slides regarding platform yet. Not all infos are released yesterday (or today for those still in the 24th).

There are no slides, because the slides are only about a Bulldozer module, not a full Zambezi CPU/chip.

However, people ask after the slide's presentation in the Q&A session about AM3 compatibility and then the AMD officials made that non-AM3 statement

[Manicdan]

honestly wtf cares about single thread performance? geez if ppl cared about it, they would not be buying dual-cores even. the whole nature of multiple cores is for multi-threading, anything else is fail!

it does have some purpose
imagine if we hear AMD say that you can have 75% of the performance at 4 threads that can have with 8 thread on BD, either it sounds like core scaling sucks, or it would mean that when 1 thread has the BD module all to itself, the bonuses are astonishing. this is very important for things that do have multi cpu support, but still have one thread limiting the others. like in games, one thread is 100% usage, the other 2 may be at 40-70% usage. so if you can give your most resource hogging thread more performance (like turboing) it can run at up to 120%, letting the other threads reach 50-90% usage.

getting the most power out of a cpu at 1, 2, 3, 4, 5, 6, 7, or all threads in a given TDP is what were are noticing both the blue and green teams are trying to accomplish, and in the end it means a WELL ROUNDED cpu.

just look at laptops, if you buy a quad u get 2ghz, if u buy a duel you get 3ghz, with proper features the quad should ALWAYS be faster than the duel, even if just 2 threads are needed. and hopefully we will be there soon enough