Howto disable the tlb-fix with CrystalCPU

[sam2008]

I am using Biostar TA770 and vista x64. The 1st bit in C0010015 is a read only bit. In some board it is 1b in some it is 0b, that's why some people is 9h and some is 8h. And this bit shouldn't affect the TLB at all. Also because the 1st bit is read only bit, so it won't matter whether you are trying to write 0b or 1b to this bit since it won't be overide and would stay at the whatever value it is set by the system. So writing a value of 0x01000019 or 0x01000018 has the same effect. This patch should be able to work for you. Try it and let me know. If it does not work, I will provide an update.

Looks good, but are you on Vista X64 and which board? State your board please, MSR hex values are different on different boards.

Vista X64 has different MSR values than 32b XP/Vista on many boards including the MSI. Each board varies, which board did you use?

MSI board doesn't have the same hex values you've wrote, so this utility won't work. It'll only work for the boards which use the above values 9h->1h and 2h->0h - caution this very clearly please. Our board needs C001_0015 EAX 8h->0h and C001_1023 EAX 2h->0h to disable the patch as I wrote above.

Can you make this slight change and update the tool?

[sam2008]

Since I am using the CrystalCPU drivers which is not developed by me, it is not meant for public use and I don't want to get any legal issue by spreading the code so that people can get around CrystalCPU. Sorry for that. But I will be glad to help if you need help to tweak other MSRs.

Can you share the source code of your app sam2008? Would be neat for other types of MSR tweaks also.

[KTE]

Sam2008, good timing, I've just tried it again and was about to post. The bit values MSI uses are different to enable and disable the patch in two BIOSes but... I've tried both these values and they give the same enable/disable change. So in effect, it should work on all boards if the MSR is the same.

[justapost]

Since I am using the CrystalCPU drivers which is not developed by me, it is not meant for public use and I don't want to get any legal issue by spreading the code so that people can get around CrystalCPU. Sorry for that. But I will be glad to help if you need help to tweak other MSRs.

Nevermind, the missing link was how to write to all the msr's in a simple way here. Just found the openlibsys project developed under the modified bsd license. That will do the job and is a project of the CrystalCPU author.

EDIT: Looking at the source "DeviceIoControl" is the windows function used to modify msr registers. "SetThreadAffinityMask" is used to choose the right core. Can be so easy.

[sam2008]

Good catch. Here is the my code that does not involve CrystalCPUID.

h_thread=GetCurrentThread();
printf("Reading Original MSR Register Status:\n");
core_mask=1;//0001 for core 1
SetThreadAffinityMask(h_thread, core_mask);

Set core_mask at 2, 4, 8 for core 2 ,3, and 4, respectively to Read/Write MSR values to each core.

Nevermind, the missing link was how to write to all the msr's in a simple way here. Just found the openlibsys project developed under the modified bsd license. That will do the job and is a project of the CrystalCPU author.

EDIT: Looking at the source "DeviceIoControl" is the windows function used to modify msr registers. "SetThreadAffinityMask" is used to choose the right core. Can be so easy.

[sam2008]

Sam2008, good timing, I've just tried it again and was about to post. The bit values MSI uses are different to enable and disable the patch in two BIOSes but... I've tried both these values and they give the same enable/disable change. So in effect, it should work on all boards if the MSR is the same.

KTE, I have updated the program anyway. Following the link below to download Ver1.02. Now for advanced users, you can change the values you want to write to MSRs in the TLB_Disable.ini file according different motherboard. For most of the users, it should work fine with the default settings. Don't change it unless the default values are causing crash on your system. When you are attempting to change the values in the TLB_Disable.ini, make sure you know what you are doing .

Link herehttp://www.rebelshavenforum.com/sis-...=000521#000000

[KTE]

Thanks sam2008. Makes me not have to mess about with code anymore. Coding is an old field of mine I stay clear of... but this coding is specific and not open to let me add any MSR I want to change in the .ini and execute that at a click. Since I have around 10 more MSR's I'll be changing regularly (C0010070/C0010062/C0010064/C0010065 - VID/FID/P-State/CnQ), I may have to digg some more code again.

[sam2008]

I got part of my code by reading the assembly code of CrystalCPU and its drivers, that part is not mine. That's why I have to use their drivers. It is not a good way and also why I don't want to disclose the CrystalCPU part.

How many MSRs you want change at a time? Would 5 MSRs enough for you? I can change the code to let you set the MSR address and values in the ini.

Thanks sam2008. Makes me not have to mess about with code anymore. Coding is an old field of mine I stay clear of... but this coding is specific and not open to let me add any MSR I want to change in the .ini and execute that at a click. Since I have around 10 more MSR's I'll be changing regularly (C0010070/C0010062/C0010064/C0010065 - VID/FID/P-State/CnQ), I may have to digg some more code again.

[Raiderman]

Thanks Sam... I have a question. I ran your patch then checked with AOD of the patch status. AOD gives me the yellow ring, and not the red one. Doesnt that mean the patch is only partially activated?

[Raiderman]

Edit: I recieved a "performance" bios from MSI that is supposed to disable the TLB, and it does the same thing. It only gives me the yellow ring. That is why I wanted to try your patch to see if it would give me the red ring on startup

[sam2008]

I read on some post saying that the Red mode is with TLB patch disabled plus AOD tweak the power saving parameters to maximize the performance. It has nothing to do with TLB patch. Someone else here might explain that better than me. So all TLB patch will just give you a Yellow ring, not Red.

[Raiderman]

OK thanks for your reply

[justapost]

I got part of my code by reading the assembly code of CrystalCPU and its drivers, that part is not mine. That's why I have to use their drivers. It is not a good way and also why I don't want to disclose the CrystalCPU part.

How many MSRs you want change at a time? Would 5 MSRs enough for you? I can change the code to let you set the MSR address and values in the ini.

Hmm tht ini file approach looks nice and easy. Best would be if you can define a mask and a value for a variable number of MSR registers.

Example:

[MSR]
C0010015_value=0x00000008
C0010015_mask=0x00000008
[MSR0]
C0010064_value=0x2C0020A0
C0010064_mask=0x00ff0000

All stuff in MSR would be applied to all cores stuff in MSR0-MSR3 whould be core specific.
App must read the MSR register, apply the mask and add add the value.

@sam2008 have you tried the msr functions in openlibsys?

int _tmain(int argc, _TCHAR* argv[])
{
	InitializeDll();
	DWORD index, eax, edx;
	index = 0xc0010071;
	RdmsrEx(index, &eax, &edx, 1);
	printf("%08X: %08X %08X\r\n", index, edx, eax);	
	DeinitializeDll();

}

Had to modify the manifest stuff to force administrative privileges but then it works.

[justapost]

Wrote a function for reading ini-File sections, rest should not be difficult eighter, but I have to di for every line I write. c++'s string mnagement is new to me.

@sam2008 do you wanna finish that ini-file proposal. I'd prefere to write a small gui app to modify p-states.

[sam2008]

@sam2008 do you wanna finish that ini-file proposal. I'd prefere to write a small gui app to modify p-states.

Spent all night working on this dann program, finally got it done. Crashed my computer several times when doing the mask debuging.



This PhenomMSR.EXE program is based on CrystalCPUID. You will need CrystalCPUID for the program to function. PhenomMSR is a free program for personal use. It is meant for studying and experimenting purposes only. The author holds NO responsibility for the consequences caused by this program. Program may not function on CPUs other than AMD Phenom (haven't tested outside Phenom). To set it up, please refer to HERE for how to properly set it up.

Use at YOUR OWN RISK!!!

Change the MSR settings in the PhenomMSR.INI file for your needs.

(1) You can read and write up to 4 MSRs at same time for all 4 cores
(2) INDEX is the address of the MSR you want to modify
(3) HIGH is the 64-33 bits of the MSR value you want to write
(4) Low is the 32-1 bits of the MSR value you want to write
(5) MASK_HIGH is the mask for 64-33 bits; MASK_LOW is the mask for 32-1 bits.
(6) If INDEX for that [MSR] is set to 0x0, the program will skip that MSR and do nothing.
(7) If MASK is set to 0x00000000, the program will directly write the values in HIGH and LOW into MSR
(8) If MASK is set to 0xFFFFFFFF, the program will basically do nothing to the original value of MSR
(9) For other cases, changing the MASK value accordingly.

Use at YOUR OWN RISK!!!

Download PhenomMSR.RAR 1.01

About the MASK
Here is the how the MASK works. If O is the original value in MSR, W is the value need to be written, and M is the mask, the logic operation is (O and M) or ((NOT M) and W).
For example, if O=01 10 00, and you want to write W=10 11 01 into the MSR but would like the 3-4 bit in the original O unchanged, then you should use M=00 11 00.
(O and M)=(01 10 01 & 00 11 00)=00 10 00
(Not M)=~ 00 11 00=11 00 11
(Not M) and W= 11 00 11 & 10 11 01=10 00 01
(O and M) or ((Not M) and W)= 00 10 00 | 10 00 01=10 10 01.
As you can see the center 2 bit as masked by M is unchanged.


[Update PhenomMSR v1.02]
Added Support for Core Masking in the INI file.
Now you can use the COREMASK to specify which core you want the MSR value to be written. It is 4-bit binary value. The lowest bit is core 1, second bit is core 2, third bit is core 3, and fourth bit is core 4. When a bit is set to 1, MSR for that core will be written. If a bit is set to zero, the program will skip the MSR for that core. For example, 0b1011 means core 1, 2, and 4 will be written, and core 3 will be skipped. If COREMASK is set to 0b1111, then the selected MSR for all four cores will be written. If COREMASK is set to 0b0000, then selected MSR won't be written to any of the cores. Changing the COREMASK value accordingly. It is set at 0b1111 by default (all 4 core enabled).


Download PhenomMSR v1.02

[sam2008]

Try using the windows function GetPrivateProfileInt(). It works better and stabler than your own code.

Wrote a function for reading ini-File sections, rest should not be difficult eighter, but I have to di for every line I write. c++'s string mnagement is new to me.

[Suosaaski]

From my testing I have come to the conclusion that with Vista SP1 the TLB-fix is enabled all the time regardless of BIOS-setting. So the fix is probably included with SP1, or at least some earlier hotfix for Vista, as it was not always enabled. So it seems that doing it via software is the only option for it.

AOD seems to disable the fix only for the first core at "red" setting. At "yellow" or "green" the fix seems to be enabled for all cores.

sam2008: I believe this program of yours needs to be run every time Windows starts up. Am I right? So if I were to make it run at startup, I would always have TLB-fix disabled?

[sam2008]

You are right. SP1 enable the patch for Phenom for stability. AOD Yellow or Red button under SP1 won't get your full speed back since it somehow only act on one core under SP1 as you noticed. That's also the reason why I decided to write a program to disable the TLB patch because it seems that is the only option.

I have the program running everytime I logon. So the patch will be disabled. For how to start up with windows follow this link HERE.
Also, if you use stand by function of the VISTA, everytime, it wakes up, it will change the TLB status to Enabled state. So you have to run the program again to disable it. But I usually shutdown when not using, so not a big problem for me.

From my testing I have come to the conclusion that with Vista SP1 the TLB-fix is enabled all the time regardless of BIOS-setting. So the fix is probably included with SP1, or at least some earlier hotfix for Vista, as it was not always enabled. So it seems that doing it via software is the only option for it.

AOD seems to disable the fix only for the first core at "red" setting. At "yellow" or "green" the fix seems to be enabled for all cores.

sam2008: I believe this program of yours needs to be run every time Windows starts up. Am I right? So if I were to make it run at startup, I would always have TLB-fix disabled?

[KTE]

sam2008: became delayed with being busy but I was going to ask exactly for four MSRs configurable in the .ini on each core.

Great work, thanks.

Will test it soon for problems. Already tried it once on XP SP3 32b, worked for first two MSRs. Saved me learning code again after years.

And yes SP1 Vista has it but it was undocumented and AMD denies it being told to MS to implement.

[LIKMARK]

The tool don't work for me, it can't read the *.dll's it says. I have of course followed the install procedures described.

[KTE]

LIKMARK: there's two tools, which one?

All work fine for me here XP SP3 32b.

[sam2008]

The tool don't work for me, it can't read the *.dll's it says. I have of course followed the install procedures described.

Did you put them in the same directory as CrystalCPUID? Also, if under Vista, you have to right click and choose to run as administrator.

[LIKMARK]

Yes, in the same directory and tried running them as admin, no luck though. Vista x64.

[Raiderman]

Thanks Sam, Everything works great, and now have full speed at startup.

[sam2008]

Is your error message "Cannot load DLL!". Can you find the Sysinfo.DLL in the same directory? I myself use x64, so should be no problem.

Yes, in the same directory and tried running them as admin, no luck though. Vista x64.