Intel Details Long-term Xeon, Itanium Plans

[StyM]

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Intel this week revealed new details about where it plans to take its server processor business, specifically with the Itanium processor. As many know, Intel took a gamble on the Itanium when it was released several years ago. Using a then uncommon Explicitly Parallel Instruction Computing (EPIC) architecture left the majority of the industry unsure of its practicality in an x86-dominated world. Today however, the Itanium family brings in roughly $3.5 billion per annun for Intel.

Diane Bryant, vice president of Intel's enterprise group, revealed several details that indicated Intel will push forward with Itanium development for the foreseeable future.

Currently, Intel's flagship Itanium 2 processor is the Montecito core. Intel announced Montecito last July, marking the company's first dual-core enterprise and mainframe processor. Until now, Montecito ran on a 533MHz front-side bus but will soon make the transition a 667MHz front-side bus processor in Q4 2007, dubbed Montvale. According to Bryant, Montvale will consist of minor updates, improving bus speed but also improving overall stability.

Recent Intel roadmaps indicate that Montvale will consist of roughly 25 percent of Intel's Itanium business in Q4 2007. By Q1 2008, Intel guidance suggests Montvale will take up a whopping 40 percent of all Itanium 2 sales. Despite Intel's desktop processors currently see day light at 65nm, Itanium 2 processors will still be on 90nm manufacturing technology. Montvale will also top out at a core speed of 1.66GHz with a total of 24MB of L3 cache.

Intel's next major milestone in the Itanium family will come with the arrival of Tukwila, a quad-core processor due sometime in late 2008. According to Bryant, Tukwila be roughly twice as fast as Montecito and feature an on-die memory controller.

This will be a turning point for Intel because with Tukwila's need for a discrete memory controller gone, the company will introduce its long waited common system interface (CSI). Tukwila's use of CSI will be a direct response to AMD's HyperTransport technology. Intel previously stated it will not restrict CSI to the Itanium family, but will eventually use the technology as the main transport bus for Xeon family as well.

Tukwila will also come with even larger caches and a new reliability feature called double device data correction (DDDC). DDDC acts as a failsafe mechanism to protect system memory failures from bringing down a live system. In a hardware failure where a memory chip on a memory module fails, DDDC will be able to mark that chip as unusable without compromising system stability. DDDC differs from traditional ECC and parity technology due to its capability to withstand more than one chip failure.

Bryant went on to reveal details about the future release of an entirely new Itanium architecture code-named Poulson. With Poulson, Bryant claims Intel will introduce even more cores; greater scalability and the introduction of 32nm die fabrication for its enterprise segment. The company will skip 45nm technology altogether for Itanium. Bryant did not give details on a possible release date for Poulson although Intel is expecting to introduce 32nm processors in approximately two years.

[XS Janus]

Intel is a steam roller R&D'er these days...

[Shintai]

DDDC looks seriously nice on the RAS side. But its not easy to say in speech.