FUN! : what's max ? BH5@1.5-0-0-0@1T ??

[hey]

just tried for fun and not maximized,, but wanna know what the hell max was done at these timings

http://valid.x86-secret.com/show_oc.php?id=195611

http://www.youtube.com/watch?v=F37FO_2SD8s

[over@locker886]

Nice

[EniGmA1987]

I did that a while ago and everyone started telling me that even though it is set that way, it isn't really running that way. Supposedly the lowest you can go is 2-2-2-5. Although it is funny that Geil makes some 1.5 CAS RAM called their Geil ONE series...

The best I could go with 1.5-0-0-0-1T @ 3v was DDR345. It was with some Ballistix. I probably could have gotten more if I put more volts into it but I already had 4 sticks of ballistix die and I don't want it to happen again.


EDIT: looks like he has the same bios as my board so he likely is using the same board I have.

[Kunaak]

nope... not real.

lowest the A64 mem controller can go, is cas 2, ras to cas 2, and TRP 2.
its in the AMD64 white papers if you want to dig it up... or find tony, he always knows where to find that kinda info.

[EniGmA1987]

It is funny that although everyone keeps saying that. I did notice a significant decrease in loading time for everything when I was running 1.5-0-0-0, even though it is technically not supposed to be capable of running at less than 2-2-2-5. Not saying your wrong, but it it possible that a change was made to newer revision CPUs and maybe the white paper wasn't updated?

[Kunaak]

not really... no.
they tend to document pretty much anything they do.
standard practice for any business that tends to be professional.

[ozzimark]

i gotta say kunaak, i agree with enigma on this one. though i don't have the data on hand, i explicitly recall 2-2-1 being faster than 2-2-2...

[EnJoY]

I know the A64 memory controller does not do any CAS latency lower than 2. However, in some Bioses, I do believe Oskar Wu managed to make CAS1.5 slightly faster than CAS2 with some tricks. At least I remember Tony mentioning something of that too me ages ago.

Also, I'm gonna have to agree with Ozzi, I do believe tRP of 1 did work, not sure about tRCD. But it would also explain why clocking is so limited when running tRP 1, as opposed to 2. Why don't you just run some bandwidth tests comparing 1.5-2-2-5, 2-2-2-5, 2-1-2-5, 2-2-1-5 and 2-1-1-5, all at the same frequency?

[oohms]

I was bored so i decided to try it:

Sempron 2600+
DFI nf3 250gb (s754)
1x256 KVR pc2700 BH-6, 3.15 volts





- Cas 1 does not post
- Trcd refused to work below 2 at 1T
- Tras made no difference to max o/c or bandwidth
- Trp 1 gives a small boost, but kills your overclock
- Not much difference between cas 2 and cas 1.5

[hey]

ok , guys let me test it ! i didnt searhed papers but here are the proofs how much that 1.5-0-0-0@1T is better than 2-2-2-5@1T ...


everest mem read, write , copy , latency @1.5-0-0-0@1T



everest mem read, write , copy , latency @2-2-2-5@1T



spi 1m 1.5-0-0-0@1T



spi 1m 2-2-2-5@1T

[EniGmA1987]

Yay
Hopefully I will have some time either tomorrow or next week where I can do some benches and get some secondary confirmation.

[hey]

Originally Posted by EniGmA1987

Yay
Hopefully I will have some time either tomorrow or next week where I can do some benches and get some secondary confirmation.

in fact , spi 1m time is really interesting but i ve tried many times

[Tony]

How can TRCD and TRP work at 0 clocks??? LOL no way

cas1.5 was something Oskar found, it does excist in theory although the A64 MC does not officially support it.

I think 0 is not quite 0, run your tests again at 1.5-1-1-1, i have a feeling they will end up the same as 1.5-0-0-0.

You are delving into the realms of the unsupported here, just because the bios says its 0 does not mean its 0,...I could rename those values to x y z just as Oskar could have as in reality he probably guessed they were 0's

Just my 2 cents...

[EnJoY]

Originally Posted by Tony

Just my 2 cents...

And if anyone can think of 2 cents that's worth more elsewhere than coming from Tony's mouth, I'd like to hear it. Those cents are worth a lot to us.

[_damien_]

I use benchmarks myself to explore and test the theoretical part of memory timings and stuff. But sometimes they have to be disregarded, and this is such an occation. Not that I believe it to be very common, but results could always be affected by different types of bugs. When one knows something to be *impossible* it would in fact be arrogant not to throw off suspicious benchmarks as irrelevant.

Concerning the "reserved" values of A64 IMCs, I partly agree to what some of you have said. At least some of those timings actually seem to work, tRP 1 being the best example I can think of.

Originally Posted by Tony

How can TRCD and TRP work at 0 clocks??? LOL no way

Basically speaking, you are obviously right, but there are other factors than parameter values that need to be considered here. If no delay is added after the assertion of tRCD (that is, added by the specific parameter value), the command-spacing would still create a one-cycle delay before the read-command would be triggered (assuming 1T command rate). The results presented by oohms show that a 2T command rate in fact adds to the delay, as tRCD 1 + CMD 1 always failed to post, while tRCD 1 + 2 CMD worked well. As the corresponding read command would be delayed by two clocks @ 2T, the effective tRCD would actually be 2 clocks - whether the tRCD setting was 0, 1 or 2 - thus preventing interaction with a corrupt row signal (unless tRCD 2 is too tight). This is one reason why an effective delay of 0 is impossible.

And to further clarify, the fact that 1T otherwise works fine, pretty much proves that the instability @ 1 tRCD + 1T is not caused by the controller having insufficient time available for address signal generation. So I think it's perfectly clear that the command rate really can affect the timings - indirectly if not directly

Originally Posted by Tony

cas1.5 was something Oskar found, it does excist in theory although the A64 MC does not officially support it.

No, it doesn't exist. BH-5 lacks the pipeline stage that would've been required for CAS 1.5 operation. In fact it only supports 2.0 and 2.5 (not even 3.0).

That said, I'm not ruling out the possibility that the use of CAS 1.5 could tighten certain sub-timings, thus improving performance, but that's a whole different story.

Originally Posted by Tony

I think 0 is not quite 0, run your tests again at 1.5-1-1-1, i have a feeling they will end up the same as 1.5-0-0-0.

They should, and the command spacing applies to this problematic topic as well. But the fact that 1.5-0-0-0 in this case performs better than 2-2-2-5 clearly suggests that something's not right here. The differences shown in the Pi and latency benches posted by hey are simply too big.

[Tony]

The only IC's I saw 1.5 working on eXpert were TCCD, it never worked for me with BH5.
To clarify, cas1.5 can excist, whether on BH5 or TCCD is another story.

Oskar looks for hidden tweaks that may improve performance, we all know that but whether they are what he labels them is another story, sometimes they are a guess and nothing more...what concerns me though is how many people believe what they see as absolute truth in a bios...this inclided Geil who marketed a whole product line on a bios value...sad is you ask me.

Anyway, best i ever did was 166 with old Micron EB at 2-1-1-1, it was actually pretty fast, much like BH5 at 2-2-2- at 200.

[_damien_]

Originally Posted by Tony

To clarify, cas1.5 can excist, whether on BH5 or TCCD is another story.

Yes, I know that CAS 1.5 is technically possible. My point was that it depends on the IC design - I am however unaware of any IC that supports it. CAS 1.5 on DDR1 seems much like CAS 2 on DDR2 - both are possible, but hardly supported (if at all).

Originally Posted by Tony

what concerns me though is how many people believe what they see as absolute truth in a bios...this inclided Geil who marketed a whole product line on a bios value...sad is you ask me.

Couldn't agree more, but at the same time I understand that people get confused. It doesn't make sense that any BIOS would provide a range of non-existent values, and I guess they include such settings hoping to seduce OC-freaks. But personally I'd rather they stuck to what's REAL...

[ziddey]

wow that's got to be t he longest load time for xp i've ever seen

[STEvil]

Werent there a few P4 boards that allowed CAS 1 on DDR?

[_damien_]

Originally Posted by STEvil

Werent there a few P4 boards that allowed CAS 1 on DDR?

Of course not. The feature may be in some BIOSes, but that's besides the point. As I have told you before, and mentioned earlier in this thread, every single CAS setting must be specifically built into the DRAM ICs in the form of pipeline stages. A CAS Read delay of 1.0 is not possible, regardless of the controller.

[STEvil]

And there has never been a DDR module designed to function at cas1, ever?

[EnJoY]

You'd think maybe there would have been at least one premium chip design for SD-RAM or DDR SD-RAM back in the old days that was capable of running lower than 2-2-2 given it's low speeds.

[hey]

ok guys , i told before , i m not saying these are really zero , none timing can be zero , just set for fun and system s worked , maybe like tony said , they re the same as 1.5 1 1 1 etc. dont have them so cant try more

[i found nemo]

Originally Posted by _damien_

Of course not. The feature may be in some BIOSes, but that's besides the point. As I have told you before, and mentioned earlier in this thread, every single CAS setting must be specifically built into the DRAM ICs in the form of pipeline stages. A CAS Read delay of 1.0 is not possible, regardless of the controller.

what about 1.5

[STEvil]

XBox uses 166mhz CAS1 SDRAM doesnt it?

Still could swear I remember people playing with CAS1 on old Asus P4 boards..