K10 can only do 64 bit stores. So for K10: 2 loads (128 bit) or 1 load and 1 store (64 bit) or 2 stores (64 bit) per cycle
Bulldozer: 2 loads and 1 store (likely 128 bit each) per cycle for each thread.
Thus BD could have about twice the L/S bandwidth per cycle compared to K10 (on average two 128 bit loads and one 128 bit store - actually 2x64 - every two cycles) when taking into account a 2R1W pattern.
One Sandy Bridge core could also do 2 loads and 1 store (128 bit each) every cycle or twice the width (256 bit) every two cycles or one 128 bit load and a 256 bit store thanks to it's 48B/cycle combined L/S bandwidth.
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JF, you talked about +50% performance for opteron with 33% more core.
We all know that performance is P=IPC x Frequency.
So It's +50% performance ? or IPC ? And it's +50% for the 12 core highest frequency opteron, or 6 cores in spec int i suppose ?
If it's performance so you must already know final frequency, and ES should already running. That's a good news. I can't wait for the 24 ^^![]()
When I saw the "50% perf increase" news spread all over the world, I found a lot of people criticized AMD “Not impressive, Intel may still on top of the world!” , “WTF were AMD doing since many years ago??”
Hey man, when the product isn't ready please don't release any negative news about the product, or it will affect the stock!![]()
Last edited by superrugal; 08-04-2010 at 03:14 AM.
superrugal: right. And never seen new CPU product with 50% more performance. If we looking at the same clock on clock, not big increase (llok at one core Core architecture vs Nehalem architecture, im talking about one core, example not big diferent q9550 one core vs i7 Nehalem one core with HTT disabled)
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If you think that 50% "for the whole chip" is not much than you need a reality check.Many applications don't scale perfectly to many cores so extracting the "single core" perf. increase out of this generic average figure is pretty much pointless(not knowing clock speeds makes it even more pointless).Not to mention this is a conservative estimate and the MC platform is drop in compatible with the BD CPUs.
My experience with numbers like these is that they are in theoretical benches like SPECint and SPECfp. So i guess the performance estimate from JF is pretty close to 50% more theoretical performance rather than practical.
BUT, I also believe that these benches are on a clockspeed that might be on the conservative side.
So if all goes well we see higher numbers than these.
Of course it is SPECint and SPECfp. I definitely trust these more than stuff like Cinebench and 3DMark CPU test.
More and more I am interested with the multithreaded performance. This single core Celeron M is getting on my nerves when doing some number crunching.
Mr. Fruehe has made a slight clarification of the 50% number in a other thread.
I sincerely hopes that by major server workloads he doesn't mean syntetic
benchmarks, but real world workload. Will be interesting to see where we end up
in the end, and if AMD has been hyping to much.
theres also the perspective that its the newest 32nm chip vs the best 45nm chip amd is offering
if we look at the growth of 45nm, we had a PII-920 and a 1055T, both 2.8ghz, both 125W TDP, but one has 50% more cores and turbo. (then we can even go farther and compare it to the 95W version, in reality, its sick how much they can improve something on the same process)
it might be a little doubtful that they can pack in more BD cores on the sever side chips, so 16 might be the max. but with better experience they will be improving that process enough that higher clocks should be expected at the same TDP across the life of 32nm BD
I'm following your thoughts, not really arguing, just putting up some more
information/clarification.
Your line ...isn't comparable with desktop workloads cannot be stressed enough.
People are using info from the server side way to literally when they are talking
desktop chips in these threads about AMD's Bulldozer architecture.
So Hot Chips finally arrives![]()
Still a few days away:
Conference Day Two: August 24, 2010 (Tuesday)
Session 7: New Processor Architectures (Session Chair: Bevan Baas, UC Davis) 5:00 - 6:30 (pm)
* The Next-generation System z Micro-Processor
Authors: Brian Curran
Affiliations: IBM
* AMD "Bulldozer" Core - a new approach to multithreaded compute performance for maximum efficiency and throughput
Authors: Mike Butler
Affiliations: AMD
* AMD's "Bobcat" x86 Core - Small, Efficient and Strong
Authors: Brad Burgess
Affiliations: AMD
IQ_NOT_LESS_OR_EQUAL
outdated hardware
Is this being covered by anyone? I mean should I expect to hear anything before Wednesday morning (or very late Tuesday night)?
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just one question
are the slides green or red?
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