AMD to Disclose Details About Bulldozer Micro-Architecture in August

[flippin_waffles]

I don't think he is really listening.

Indeed. Its also equaly clear what his/her intent is as there's too much interest in bulldozer, and they can't lose the mindshare battle and performance battle. Imagine if that were to happen, it would be devistating!

[Dresdenboy]

and theres a huge chance the clocks are higher, as magny cours runs at 1.9-2.3ghz

It could be more complicated than that: Which clock will be higher? Integer Core clock? FPU clock? Front end clock? We don't know enough to include clock frequency into considerations. Same with IPC, since performance analysis based on it depends on clock frequency.

We even don't know the scaling behaviour and which power redistribution strategies a feature called APM Boost might use to get the most performance out of an app.

[freeloader]

AMD did good with the transition from 0.25µ to 0.18µ, but since then they have lagged behind. And since 0.13µ have they been saying that with the next transition they should be gaining on Intel. They haven't, so far.

If AMD had the same resources (ie MONEY) as Intel, then they'd be giving Intel a run for it's money.

Anyhow, on topic. We will just have to wait for BD benchmarks. Personally I'm taking a conservative approach and believe BD will be roughly 20% faster clock for clock than a comparable Phenom II core.

[flippin_waffles]

He was talking about an old slide, not about today.

I dunno when they'll show up, but 6 months is optimistic, maybe 10-12 months. On the other hand, an AMD representative said in a BS-news interview that their 32 nm process is only 3 months behind Intel, although I find that hard to believe.

Could very well be true, they just might not be talking about 1 or 2 percent of total volume like intel likes to do. And with the trouble intel seems to be having with they're attempt, it doesn't look like a very mature process.
AMD has always been quicker to a mature process and crossover point, so by the time intel gets their issues and volume sorted out, AMD won't be very far behind at all.
We've all heard the superior process propoganda from the blue camp, ad nauseum. 45nm without HKMG being impossible, is one that springs to mind. Yet here we are with AMD's advanced SOI process with ultra lowK dielectrics, proving that most of intels talking points are dust in the wind.

[savantu]

It could be more complicated than that: Which clock will be higher? Integer Core clock? FPU clock? Front end clock? We don't know enough to include clock frequency into considerations. Same with IPC, since performance analysis based on it depends on clock frequency.

Where did you find they will be different ? It's one thing to have different clock domains for the core and uncore parts, it is an order of magnitude more complicated to have inside the core, especially between front end and back end. While running the ALUs at double the core frequency was done in the past ( Netburst ), I remember this was dropped because the added complexity wasn't worth it. It would be nice if AMD would try its hand at this, the simpler integer cores from BD might be suitable for such an endeavor. regarding the FPU units; with the introduction of AVX and 256 bit datapaths, I really doubt anyone is thinking of mixing with frequency.

I would imagine its clock distribution wouldn't be extremely agressive, they are introducing too many innovations already, why raise the risk ?

The disaster with SUN Rock comes to mind, also 16 cores, 45nm, scout threads, it ended up using 250+ watts and had one spectacular merit : it was a complete dog.

We even don't know the scaling behaviour and which power redistribution strategies a feature called APM Boost might use to get the most performance out of an app.

What else can be different than what Intel does today ? Constantly check power usage and temperature and if you are within limits, up the frequency. This is the simplest ( from a theoretical POV, not implementation ) and most effective way.

Could very well be true, they just might not be talking about 1 or 2 percent of total volume like intel likes to do. And with the trouble intel seems to be having with they're attempt, it doesn't look like a very mature process.
AMD has always been quicker to a mature process and crossover point, so by the time intel gets their issues and volume sorted out, AMD won't be very far behind at all.

What trouble ? Please share with us your information. From everything that I've seen, Intel's 32nm is flawless with state of the art performance. Btw, from where do you get your 1 or 2% of total volume ? 32nm is far higher than that right now.

We've all heard the superior process propoganda from the blue camp, ad nauseum. 45nm without HKMG being impossible, is one that springs to mind. Yet here we are with AMD's advanced SOI process with ultra lowK dielectrics, proving that most of intels talking points are dust in the wind.

Probably that why the Fishkill alliance is sweating continously to get hkmg into production; I know..they've swallowed the "propoganda".

[-Boris-]

If AMD had the same resources (ie MONEY) as Intel, then they'd be giving Intel a run for it's money.

Anyhow, on topic. We will just have to wait for BD benchmarks. Personally I'm taking a conservative approach and believe BD will be roughly 20% faster clock for clock than a comparable Phenom II core.

Yes I know, process transitions is all about money. It's expensive, but saves money in the end. The larger the production the more money saved. So it's easier for Intel to put more money in it to get it done earlier.

And I am hoping that Bulldozer will help AMD to dominate the performance market the next five years or so. But I doubt it more and more. Since Yonah, everything Intel have done is great, while AMD struggles.

[cegras]

I think you missed these:

What does "50% greater total throughput" mean? Int? FP? Both? Average? You say this is now the only official projection, I would just like to understand what it means.

Are you saying that the 60-80% greater specInt_rate was MC to Istanbul, rather than Interlagos to MC? (I didn't say anything about a voiceover...) I guess it must be, if you were not committing to any Interlagos percentages at that time. Shouldn't you let Johan @ Anandtech know to correct his article?

--------------------

Ok, so you are claiming that despite the numerical scale, the part of the chart that contains future projections (MC and Interlagos) was only directional? And that this was obvious to everyone in the room.

And yet, the MC data on the chart was nearly bang-on with what was promised, even if you overdelivered a bit. And yet the chart has a disclaimer, specifically talking about the MC & interlagos data points, calling them projections. Wouldn't that say "directional only", instead? Wouldn't the scale stop at the 2435 level instead of continuing up linearly through the range of everything else? Color me skeptical, but ok.

But could you please clarify the 2 things in the top section?

He has no obligation to clarify. Stop asking. If that is all he is going to say you have no right to ask for more.

Also, is it that hard of an intellectual leap that data for real parts would be drawn somewhat accurately, while 'data' (read: projections) for in production parts be left as directional?

[Dresdenboy]

Where did you find they will be different ? It's one thing to have different clock domains for the core and uncore parts, it is an order of magnitude more complicated to have inside the core, especially between front end and back end. While running the ALUs at double the core frequency was done in the past ( Netburst ), I remember this was dropped because the added complexity wasn't worth it. It would be nice if AMD would try its hand at this, the simpler integer cores from BD might be suitable for such an endeavor. regarding the FPU units; with the introduction of AVX and 256 bit datapaths, I really doubt anyone is thinking of mixing with frequency.

I would imagine its clock distribution wouldn't be extremely agressive, they are introducing too many innovations already, why raise the risk ?

The disaster with SUN Rock comes to mind, also 16 cores, 45nm, scout threads, it ended up using 250+ watts and had one spectacular merit : it was a complete dog.

There is a presentation by Chuck Moore, where he wrote up about the same statements he's presented later, while already at AMD:
http://www.ece.rochester.edu/~albone...ides/moore.pdf

One of the possible ways to evade to is to go to a cycletime, where instruction throughput (per unit time) peaks. Most of today's IPC is achieved by increasing complexity, thus increasing die area (and ever increasing static leakage) and limiting cycletime (or even decreasing without new processes), which means nearly stagnating clock frequencies. What if design gets simplified (lowering IPC), but allows for 20% or more area savings and increasing clock frequency (without having to increase voltage, since less complex circuitry does the job faster). Well, this is just one idea.

Having different clock domains in a module would allow to choose closer to optimal cycle times for different units, also driven by the type of work to do. E.g. decoding could have a longer pipeline if some trace caches and good branch prediction is present. A shared FPU would also be a candidate for a longer pipeline while integer cores could benefit from a short schedule execute loop and be clocked lower, but be 4-wide. There are so many possible techniques...

I didn't see any clear signs for such stuff except for some flexible clock generator modules or a FPU running at a different clock (and adapting it to the workload) than the integer execution units and maybe some others..

What else can be different than what Intel does today ? Constantly check power usage and temperature and if you are within limits, up the frequency. This is the simplest ( from a theoretical POV, not implementation ) and most effective way.

What can be different are the granularity and the units themselves.

Granularity: power down/up, clock differently the different subunits, as power budget permits and queue fill level requires

Units: scale them to what fits best and optimize power usage this way.. e.g. switch off some L2 cache ways or execution units
or activate them as needed (by tracking the upcoming instructions and powering up/clocking the appropriate subunits).

[terrace215]

He has no obligation to clarify. Stop asking. If that is all he is going to say you have no right to ask for more.

Also, is it that hard of an intellectual leap that data for real parts would be drawn somewhat accurately, while 'data' (read: projections) for in production parts be left as directional?

2nd first: I finally see what he was trying to say regarding the fading.

---

Why should I stop asking? He's said, "the only performance projection we are making at this time is [X]." The trouble is, it is unclear to me (do YOU understand?) what the heck X means. If they are really making some projection at this time, why WOULDN'T he clarify what it means?

In addition, he posted here, back in November:
http://www.amdzone.com/phpbb3/viewto...?f=52&p=172169

JF-AMD wrote:

AussieFX wrote:
Exactly.
What I want to know is how does Anand know Interlagos is 60-80% faster than MC? He has NO fscking idea.

He knows that because I told him that.

Magny Cours = 50-60% faster than Istanbul

Interlagos = 60-80% faster than Magny Cours


Both of these are conservative estimates which I personally believe are too low, but I don't get to make the call on that.

JF posted that on Nov 25, 2009, regarding Johan saying Interlagos integer throughput was 60-80% higher than MC. Said it was conservative! That puts Interlagos SpecInt_rate(base) at... 556!

Given that this is MUCH DIFFERENT than "we have only ever said 50% greater 'total throughput'", and "we were not making specific projections then because we had no idea", I'd like to know if this was a mistake, true, or what.

[cegras]

He personally believes. Did you ever read his signature? His posts are personal opinions.

[FlanK3r]

dont ofenzive at people please, but normal discussion to thema...

[LightSpeed]

Why should I stop asking?

Because he asked you to stop asking about slides which have fading bars, and quotes which were made around 2 years before the CPU release date. Those slides were NOT exact, and those quotes can certainly change given that a lot can change in 6 months time. Dont you agree?

A 16 "Core" (16Int, 8FP) Bulldozer will be 50% faster than a 12Core Magny Cours. Maybe the 60-80% changed into 50% because Magny Cours overdelivered? Maybe its being more conservative, or some reason entirely different. But thats the latest quote, maybe you should break that down and discuss instead of diving into old quotes and graphs with faded bars?

[terrace215]

He personally believes. Did you ever read his signature? His posts are personal opinions.

Oh, BS. When he posts performance claims about Bulldozer in a forum, it's obviously not some "personal belief" completely detached from his inside information, regardless of any disclaimer. If it were, it would be akin to "making things up", and what use would that be?

At this point I'm trying to resolve 2 things from his own posting history:

(1) What does "total throughput" mean? If the only performance claim AMD is making at this time is "Interlagos has 50% greater total throughput than MC", wouldn't you like to know what that even means?

(2) He's said the fading performance projections slide (*apparently* showing 50% greater fp throughput, 26% grater int throughput) for Interlagos was merely meant to say, "we are not making any actual projection at this time, other than it will be greater than MC". Ok, fine, let's accept that. In addition he says that in fact, they would not even be able to project accurately at that time, as it was too early. Ok, accept that too. And yet... at the very same time, he posts that he told Anandtech that Interlagos would have 60-80% higher throughput (specifically specInt_rate) than MC, and that this was conservative!

See the contradiction here? He says, "X" to one person 6 months ago, tells another they couldn't possibly predict "Y" back then, and didn't mean to suggest "Y" at all, and says the only claim they are making is "Z", which isn't even very well defined! And "X" "Y" and "Z" contradict one another.

It's all over the place. And sometimes, when you ask about these issues, the answer is, "Oh *I* never disclose -blah-, only AMD can officially do that", even though he HAS been posting precisely about -blah- all over the forums.

Crazy.

If he simply said, "We never intended Y" (he has done this), "X was a mistake/is withdrawn/is no longer accurate" (he has not done this), and "Z means ...." (he has not done this), then everything would be quite clear.

Note that I am not asking him to disclose more than he/AMD already have. I'm asking him to resolve the inconsistencies between the various things he's said, and in one case (Z), define a term that he used.

[terrace215]

Maybe the 60-80% changed into 50% because Magny Cours overdelivered? Maybe its being more conservative, or some reason entirely different. But thats the latest quote, maybe you should break that down and discuss instead of diving into old quotes and graphs with faded bars?

Lucky for you, these are precisely the 2 things I am asking him about now!

[informal]

I think JF is just being cautious here while he states the "50% better claim". AMD certainly knows by now where Interlagos will land performance wise,but JF can't say the exact number because,well there is no exact number since the launch is still in 2011.A lot can change and I believe it will change for the better,meaning Interlagos will overshoot the conservative estimate JF gave by a large margin. We will definetlly have more information in August ,with teh Official Bulldozer blog coming up and the Hot Chips and Analyst day events.Until then one can decipher the fading bars on an old chart all day long,only the thing is he will find zero relevant information...

[Manicdan]

this is why people need to not get emotional until benchmarks are out. theres too many new features that have to work together, and alot of unknowns just from the fab process, to really give off anything near accurate, unless A your able to predict the future, or B, insane.

many of us are happy to have someone on the inside of AMD to talk too about things. please dont scare him away because hes not a future teller.

[cegras]

Oh, BS. When he posts performance claims about Bulldozer in a forum, it's obviously not some "personal belief" completely detached from his inside information, regardless of any disclaimer. If it were, it would be akin to "making things up", and what use would that be?

At this point I'm trying to resolve 2 things from his own posting history:

(1) What does "total throughput" mean? If the only performance claim AMD is making at this time is "Interlagos has 50% greater total throughput than MC", wouldn't you like to know what that even means?

(2) He's said the fading performance projections slide (*apparently* showing 50% greater fp throughput, 26% grater int throughput) for Interlagos was merely meant to say, "we are not making any actual projection at this time, other than it will be greater than MC". Ok, fine, let's accept that. In addition he says that in fact, they would not even be able to project accurately at that time, as it was too early. Ok, accept that too. And yet... at the very same time, he posts that he told Anandtech that Interlagos would have 60-80% higher throughput (specifically specInt_rate) than MC, and that this was conservative!

See the contradiction here? He says, "X" to one person 6 months ago, tells another they couldn't possibly predict "Y" back then, and didn't mean to suggest "Y" at all, and says the only claim they are making is "Z", which isn't even very well defined! And "X" "Y" and "Z" contradict one another.

It's all over the place. And sometimes, when you ask about these issues, the answer is, "Oh *I* never disclose -blah-, only AMD can officially do that", even though he HAS been posting precisely about -blah- all over the forums.

Crazy.

If he simply said, "We never intended Y" (he has done this), "X was a mistake/is withdrawn/is no longer accurate" (he has not done this), and "Z means ...." (he has not done this), then everything would be quite clear.

Note that I am not asking him to disclose more than he/AMD already have. I'm asking him to resolve the inconsistencies between the various things he's said, and in one case (Z), define a term that he used.

If that's the only claim they are making, you should connect two and two and come to the conclusion that that is the *only* claim they wish to make at this time. You won't get more, and you have no right to ask for more.

[terrace215]

If that's the only claim they are making, you should connect two and two and come to the conclusion that that is the *only* claim they wish to make at this time. You won't get more, and you have no right to ask for more.

What you're saying is that I should assume he is (by implication) withdrawing the claim X (the Johan claim). I'm merely asking for confirmation.

As for "the only claim", I'm trying to understand what it means. Perhaps a specific example would help:

---
Suppose that NEW_CHIP has 25% better integer throughput, and 75% better FP throughput, than OLD_CHIP.

Would JF say that NEW_CHIP's "total throughput" was:

25% (the min)
50% (the average)
75% (the max)
100% (the "sum" of 25 and 75)

better than OLD_CHIP?
---

How is he defining "total throughput" in terms of int and fp throughput (for which folks commonly use the spec_rate benches)?

Without this being defined, the "only performance claim AMD is now making" is close to useless, as could imply a very large actual performance range. (Could mean int and fp each 25% greater, could mean fp 50%, int 100% greater-- that's a HUGE difference.) You see what I mean? It makes the "50%" fairly useless without a more precise definition. Might as well say, "greater throughput than MC", or, even, "we are making no performance claims at all at this time."

JF can choose to answer or not. I doubt he needs a fanbase to protect him from questions in the very forums he comments in, so what's with all these people saying, "stop asking him [to clarify] things [that he posted]!!!!!!111" ??

[superrugal]

Frankly speaking, I don't entirely believe JF-AMD.

[Mats]

It's really not that hard too see: If he could tell us more then he would already have done it. Yes, JF haven't given a complete answer, but I'm not sure that you'll get one just because you ask five times.

[terrace215]

It's really not that hard too see: If he could tell us more then he would already have done it. Yes, JF haven't given a complete answer, but I'm not sure that you'll get one just because you ask five times.

Your avatar is... why is that red-skinned person shoving a skyscraper up their backside?

[Helmore]

@terrace - Ever considered the fact that he might even lose his job for relaying too much information about future products? AMD doesn't want to give Intel any clues at all about Bulldozer, not until they started selling the chips. AMD is in a tough position though, they're the underdog and have to please their investors. That's why AMD has to show that something better is coming in 2011, they just don't want Intel to have any idea how much better. A year is a long time and if Intel did know exactly how Bulldozer will perform then they can adjust their future plans to better compete with it.

It's really simple, AMD needs to please its investors without giving Intel any clues whatsoever and that's a bit of a problem.

[LightSpeed]

Lucky for you, these are precisely the 2 things I am asking him about now!

Man, give it a break. Maybe it will be great, maybe itl be so so. Wait till the launch, and ffs dont jump on faded graphs and old quotes

[haylui]

Your avatar is... why is that red-skinned person shoving a skyscraper up their backside?

lol
man you have a serious perception error
btw, I don't understand you simple predict from the presentation chart; that ain't precision/accurate chart, so stop speculating and extracting information out of such presentation chart.
stop doing such simple calculation here and assume BullDozer would scale in linear way. Most of the time, the scaling is non-linear(if you understand what i mean)

let me remind you, his avatar is a red sun and the yellow thingy was a building, asian style building.

[terrace215]

Man, give it a break. Maybe it will be great, maybe itl be so so. Wait till the launch, and ffs dont jump on faded graphs and old quotes

If my speculation & questions about JF's previously posted information on an upcoming product upset you, maybe ignore my posts, this thread, etc?