AMD to Disclose Details About Bulldozer Micro-Architecture in August

[terrace215]

No, you are completely wrong here.


PLEASE DELETE THAT CHART.

I have explained several times:

1. The chart was drawn in powerpoint, the chart was not done in excel where you would have exact numbers

Edit: you mean the projected numbers? The historical numbers on the chart look VERY accurate.
For example:
2435 2-socket Spec_rate base performance is Int: 160, Fp: 128.

Now look at that chart: I'll be damned if the "integer performance" bar isn't at 16, and the the "floating point performance" bar looks just like... wait for it... 12.8 ! Pretty good accuracy, even in power point!

The values are very close to 2-socket int and fp spec-rate base data for the all historical data points after 2006. Like +/- 5% close.

Yet you claim I am "completely wrong here." Well, let's just say that 2-socket spec2006-rate divided by 10 is an EXCELLENT proxy for the historical performance data shown on that slide.

Besides, what else would make sense for "integer" and "floating point" throughput, that you would have handy for all those processors, other than spec rate benches?

2. The chart uses a fade to purposely hide the actual performance estimates because we were not making actual estimates at the time.

The fade provides a range. Are you saying even the range is deliberately inaccurate? That is AMD's official position? That despite the slide saying, "Interlagos data based on AMD projections" it was NOT a good-faith estimate at the time? Given that it hasn't been officially corrected or withdrawn (that I know of), that seems unlikely.

Anyone that obsesses about that chart would also notice that the Magny Cours performance increase over Istanbul was also underestimated.

Indeed, I pointed that out, that the chart showed MC performance under where it ended up. Which fits with your oft-repeated claim to have underpromised/overdelivered on MC.

If you want to refer to any performance estimate for bulldozer, there is one official one: 50% greater total throughput than Magny Cours.

Let me make sure I completely understand this:

You are saying that AMD's official position is now that the slide shown at Analyst Day 2009 projecting Interlagos performance has been *withdrawn* as a claim, and that the only claim AMD is officially now making is "50% greater total throughput than Magny Cours".

When did AMD officially withdraw the A Day 2009 performance projections?

What does "50% greater total throughput" mean?

Is that Integer? FP?

An average of those two? Both of them, independently?

We won't be saying anything else for the forseeable future.

Any other guess, no matter how complicated the math or methodology, will be wrong.

Well, this may be stating the obvious, but a correct guess would not be wrong.

And since you won't be saying anything else for the foreseeable future, you'll have to excuse us for speculating based on official AMD presentation materials. Unless you are saying AMD has OFFICIALLY withdrawn Bergman's slide? Is that what you are saying?

They still host that presentation slide on the amd website, you know...


--------------

Until AMD provides new official performance projections, or actual benchmarks, or something more than "total throughput 50% more than MC" (or defines that term), I'll stick with what I think that chart showed:

Interlagos top-bin 2-socket spec2006int_rate(base): 360-390 (projection)
Interlagos top-bin 2-socket spec2006fp_rate(base): 400-430 (projection)

Now, that just happens to be about 50% greater *FP* throughput than MC (int 309, fp 290) at the top end, so evidently that part isn't completely wrong!
It's the integer part that the chart suggests is at most 25% greater throughput than MC. I don't know what to say, are you saying that the chart is wrong *here*? That the integer throughput is also 50% greater, contra the chart?

What about you posting that you told Johan that specInt_rate was 60-80% higher? Was that a mistake, too? Are you withdrawing that? It applied to something else? Or sticking by it?

FYI, 50% higher int throughput would be: 463 (!) 60-80% higher int throughput would be 494-556 (!!). Those would be rather better than the chart showed, the last being almost unbelievably high at the top (80% improvement) end.

[JF-AMD]

We are not withdrawing anything. That slide was an estimate and it was purposely drawn not to scale. It was directional. Trust me, everything goes past the lawyers, they are not going to be comfortable with an exact measurement being displayed if we do not have the parts to test.

Nobody would ever give a numerically accurate chart almost two years before the product hits the market.

The voiceover from the analyst meeting was about the comparison of Magny Cours to Istanbul. The Interlagos bars were added to show that there would be another large increase of performance in the same socket. That is specifically why they are fading; we were committing to AN increase, not a percentage.

At the time it was clear to everyone in the room that this was directional and designed to indicate an increase in performance and not exact. Sorry that everyone has spent so much time deconstructing that chart, it was never meant to be viewed from that perspective.

I have covered this slide on several occasions, each time telling people this was directional and not exact.

[Stukov]

We are not withdrawing anything. That slide was an estimate and it was purposely drawn not to scale. It was directional. Trust me, everything goes past the lawyers, they are not going to be comfortable with an exact measurement being displayed if we do not have the parts to test.

Nobody would ever give a numerically accurate chart almost two years before the product hits the market.

The voiceover from the analyst meeting was about the comparison of Magny Cours to Istanbul. The Interlagos bars were added to show that there would be another large increase of performance in the same socket. That is specifically why they are fading; we were committing to AN increase, not a percentage.

At the time it was clear to everyone in the room that this was directional and designed to indicate an increase in performance and not exact. Sorry that everyone has spent so much time deconstructing that chart, it was never meant to be viewed from that perspective.

I have covered this slide on several occasions, each time telling people this was directional and not exact.

I don't think he is really listening.

[terrace215]

We are not withdrawing anything. That slide was an estimate and it was purposely drawn not to scale. It was directional. Trust me, everything goes past the lawyers, they are not going to be comfortable with an exact measurement being displayed if we do not have the parts to test.

Nobody would ever give a numerically accurate chart almost two years before the product hits the market.

The voiceover from the analyst meeting was about the comparison of Magny Cours to Istanbul. The Interlagos bars were added to show that there would be another large increase of performance in the same socket. That is specifically why they are fading; we were committing to AN increase, not a percentage.

At the time it was clear to everyone in the room that this was directional and designed to indicate an increase in performance and not exact. Sorry that everyone has spent so much time deconstructing that chart, it was never meant to be viewed from that perspective.

I have covered this slide on several occasions, each time telling people this was directional and not exact.

I think you missed these:

What does "50% greater total throughput" mean? Int? FP? Both? Average? You say this is now the only official projection, I would just like to understand what it means.

Are you saying that the 60-80% greater specInt_rate was MC to Istanbul, rather than Interlagos to MC? (I didn't say anything about a voiceover...) I guess it must be, if you were not committing to any Interlagos percentages at that time. Shouldn't you let Johan @ Anandtech know to correct his article?

--------------------

EDIT:

Oh, I think I finally get it. The fading was intended to indicate not a range, but rather "unknown at this time" (other than "more than MC").

But could you please clarify the 2 things in the top section?

[-Boris-]

your point is???

This is my point.

http://www.anandtech.com/show/846/7

5 years of development don't guarantee .

Hexacores at 2 GHz ?
New games that need performance will take advantage of parallel execution.

Of course, but more cores will never be more important than more speed per core. A chip with 50% more cores will never perform as good as a chip with 50% more speed per core in games.

And that is why it's so important to have better performance per core in bulldozer.

If you want to refer to any performance estimate for bulldozer, there is one official one: 50% greater total throughput than Magny Cours.

We won't be saying anything else for the forseeable future.

12% per core is really weak. That won't even compete with i7s from 2008. That isn't even as big as the difference between Phenom and Phenom II, or between Athlon 64 and Phenom. Or even Xp to Athlon 64. I don't think I've seen such a weak boost in a new architecture from AMD ever.

I really hope that there are bigger performance gains than that.

[superrugal]

12% per core is really weak. That won't even compete with i7s from 2008. That isn't even as big as the difference between Phenom and Phenom II, or between Athlon 64 and Phenom. Or even Xp to Athlon 64. I don't think I've seen such a weak boost in a new architecture from AMD ever.

I really hope that there are bigger performance gains than that.

The engineer said, when the second integer core is actived, it will gain 80% performance increased. I write a simple formula below:

(100%+50%)*6*x = (100%+80%)*4*y

x stands for one core performance of K10
y stands for one integer core performance of bulldozer

The result is : 1.25x=y. So bulldozer will stronger than K10 about 25% in single core performance.

If I was wrong please correct me.

[generics_user]

This is my point.

http://www.anandtech.com/show/846/7

5 years of development don't guarantee .



Of course, but more cores will never be more important than more speed per core. A chip with 50% more cores will never perform as good as a chip with 50% more speed per core in games.

And that is why it's so important to have better performance per core in bulldozer.



12% per core is really weak. That won't even compete with i7s from 2008. That isn't even as big as the difference between Phenom and Phenom II, or between Athlon 64 and Phenom. Or even Xp to Athlon 64. I don't think I've seen such a weak boost in a new architecture from AMD ever.

I really hope that there are bigger performance gains than that.

while BD has 50% more cores (16 cores / 8 modules); 2 cores share some execution units and performance / core will drop once all cores are fully utilized (80% gain with a module / 2 cores compared to 100% with 2 completely seperated cores); i expect at least a 20% improvement with BD in single-threaded apps

[Dresdenboy]

I still see many posters assuming that BD cores are somehow comparable to MC cores and just need some adjustment factors. But this might lead to high error margins. But a lot might change. Just have a look at a presentation held by Chuck Moore in 2003:
http://www.ece.rochester.edu/~albone...ides/moore.pdf

Besides the description of the TRIPS architecture, it contains some key arguments for designing a future CPU (including the last slide).

Also readers of my blog should already know, what topics people related to Bulldozer are involved in.

I think due to the changes in the architecture there is some significant headroom on the compiler side, more than for an evolved architecture. This might become a P4 like situation.

[savantu]

The engineer said, when the second integer core is actived, it will gain 80% performance increased. I write a simple formula below:

(100%+50%)*6*x = (100%+80%)*4*y

x stands for one core performance of K10
y stands for one integer core performance of bulldozer

The result is : 1.25x=y. So bulldozer will stronger than K10 about 25% in single core performance.

If I was wrong please correct me.

You didn't factor any frequency gain. AMD is constantly comparing BD on energy efficiency and throughoutput with MC, doesn't say a word on IPC improvements.

A MC cpu has 12 integer cores and 12 floating point units; a BD cpu will have 16 integer cores ( a bit simpler than MC ) and 8 floating point units ( 2x de throughoutput of MC units when AVX is used - thus more complex FP)

If BD clocks 25% faster ( 2.7Ghz which isn't out of reach if 32nm works ) than you end up with no IPC improvement.

[-Boris-]

The engineer said, when the second integer core is actived, it will gain 80% performance increased. I write a simple formula below:

(100%+50%)*6*x = (100%+80%)*4*y

x stands for one core performance of K10
y stands for one integer core performance of bulldozer

The result is : 1.25x=y. So bulldozer will stronger than K10 about 25% in single core performance.

If I was wrong please correct me.

I was just calculating on the numbers JF-AMD gave me. And stating that I hope for much greater performance increases.

while BD has 50% more cores (16 cores / 8 modules); 2 cores share some execution units and performance / core will drop once all cores are fully utilized (80% gain with a module / 2 cores compared to 100% with 2 completely seperated cores); i expect at least a 20% improvement with BD in single-threaded apps

What you are saying is that Bulldozer will loose relative performance in multithreaded applications. That's the opposite of what AMDs claims.

If AMD talks about multithreaded performance all the time, it's reasonable to believe that it's in this field that BD will be making the greatest improvements: And if JF-AMD is correct when he says 50% higher total throughput with 33% more cores, that means 12.5% higher performance than MC per core in the area that Bulldozer was supposed to shine.
My question is, if that is the case, how is the performance in the scenarios AMD don't talk about?

[superrugal]

You didn't factor any frequency gain. AMD is constantly comparing BD on energy efficiency and throughoutput with MC, doesn't say a word on IPC improvements.

A MC cpu has 12 integer cores and 12 floating point units; a BD cpu will have 16 integer cores ( a bit simpler than MC ) and 8 floating point units ( 2x de throughoutput of MC units when AVX is used - thus more complex FP)

If BD clocks 25% faster ( 2.7Ghz which isn't out of reach if 32nm works ) than you end up with no IPC improvement.

Well......you forget the memory increased.
Bulldozer will support DDR3-1866, K10 only support DDR3-1333, so if you use DDR3-1333, and lower frequency model, the Bulldozer will be worse than K10 in single thread. Right???

[Calmatory]

Well......you forget the memory increased.
Bulldozer will support DDR3-1866, K10 only support DDR3-1333, so if you use DDR3-1333, and lower frequency model, the Bulldozer will be worse than K10 in single thread. Right???

Yes, and if you use loose timings then the IPC will be lower again. And with hand-picked benchmarks, BD can go very low in terms of IPC and overall performance.

Looks very bad for AMD!

Oh wait..

[Mats]

Well......you forget the memory increased.
Bulldozer will support DDR3-1866, K10 only support DDR3-1333, so if you use DDR3-1333, and lower frequency model, the Bulldozer will be worse than K10 in single thread. Right???

Aren't you mixing up server with desktop now? Even if Interlagos support DDR3 1866 ECC, I haven't seen any proof that it's was used for that [50 %] comparison. If ECC 1866 exists at all.

This is the kind of meaningless speculation I'm talking about, people make assumptions that suits their opinion. Wait until we see at least a couple of benchmarks.

Right now we have just as much information as when Randy Allen said Barcelona would be 40 % faster than Cloverton, and we all know how that ended.

[Dresdenboy]

If AMD talks about multithreaded performance all the time, it's reasonable to believe that it's in this field that BD will be making the greatest improvements: And if JF-AMD is correct when he says 50% higher total throughput with 33% more cores, that means 12.5% higher performance than MC per core in the area that Bulldozer was supposed to shine.
My question is, if that is the case, how is the performance in the scenarios AMD don't talk about?

AMD didn't talk about Zambezi, but about Interlagos. Interlagos is a server MPU and the targeted audience wanted to hear about server stuff. Some of them would even buy Atom based supercomputers (like the Transmeta Crusoe based one in the past). They're not that much interested in single core or desktop app performance.

It's a situation like with Thuban. No data.

Instead we can look, what ideas the people involved in developing BD or BC could have brought in, like adaptivity or high frequency (see Moore's 8 FO4 design - K10 is ~23 FO4). There is a thermal budget and CPU design's don't have to be static (and designed for the worst case).

Let's imagine a 16C Interlagos with ~100W TDP. This could mean ~2x15W for uncore, leaving ~70W for 16 cores or about 4W per core (8W per module). An 8C Zambezi with 100W would have 1x15W uncore and nearly 11W per core (21W per module). This could be used for frequency increases compared to Interlagos.

[madcho]

We are not withdrawing anything. That slide was an estimate and it was purposely drawn not to scale. It was directional. Trust me, everything goes past the lawyers, they are not going to be comfortable with an exact measurement being displayed if we do not have the parts to test.

Nobody would ever give a numerically accurate chart almost two years before the product hits the market.

The voiceover from the analyst meeting was about the comparison of Magny Cours to Istanbul. The Interlagos bars were added to show that there would be another large increase of performance in the same socket. That is specifically why they are fading; we were committing to AN increase, not a percentage.

At the time it was clear to everyone in the room that this was directional and designed to indicate an increase in performance and not exact. Sorry that everyone has spent so much time deconstructing that chart, it was never meant to be viewed from that perspective.

I have covered this slide on several occasions, each time telling people this was directional and not exact.

I agree, it's to early to speak about charts and numbers. But i seriously hope, we're not going to wait 2 years ...

I don't want be grandfather before AMD get back the race.

We need more FX ships, and i hope AMD will deliver us a super high end dual opteron for us.

BD cores are wider ( 4 issues ), and we can be sure AMD improved IPC with newer prediction systems. And We all know the performance depands on frequency.

So Even if we know the ipc improvement, we can't know the performance of the ship without knowing frequency, that we can't know now.

So we waited 5 years, we can wait 6 months

[FlanK3r]

Dresden: off question, do u think, was to Thuban using low-K process?

logical is clear, high-end Bulldozer will better than top Thubans...And we will see now, how Thuban great are. And SB? To time i seen 2 comparsion-Intel promotion and coolaler practice job. In mostly wiil not SB to much better than Nehalems. So...?

[-Boris-]

AMD didn't talk about Zambezi, but about Interlagos. Interlagos is a server MPU and the targeted audience wanted to hear about server stuff. Some of them would even buy Atom based supercomputers (like the Transmeta Crusoe based one in the past). They're not that much interested in single core or desktop app performance.

It's a situation like with Thuban. No data.

Instead we can look, what ideas the people involved in developing BD or BC could have brought in, like adaptivity or high frequency (see Moore's 8 FO4 design - K10 is ~23 FO4). There is a thermal budget and CPU design's don't have to be static (and designed for the worst case).

Let's imagine a 16C Interlagos with ~100W TDP. This could mean ~2x15W for uncore, leaving ~70W for 16 cores or about 4W per core (8W per module). An 8C Zambezi with 100W would have 1x15W uncore and nearly 11W per core (21W per module). This could be used for frequency increases compared to Interlagos.

Of course, but they compare to Magny Cours, which is to Thuban what an Interlagos is to Zambezi. I don't see any reason why the frequency and performance difference between Interlagos and Zambezi would be any different than that of Magny Cours and Thuban.

So if the 12.5% per core increase between Magny Cours and Interlagos is correct, It's reasonable to believe that the difference between Thuban and Zambezi will be something similar.


There is much news in Bulldozer, and it will be interesting to see how new the chip actually is. I hope it's brand new, but I don't trust AMD completely when they say so. Turion was supposed to be designed from the ground up for laptops according to their marketing people.
But even if it's completely new with a hundred new three letter acronyms, it won't matter if we see such bleak performance advantage to Phenom II.
With a bit of luck even Liano will be in the same league as quadcore Zambezi.

[Mats]

I agree, it's to early to speak about charts and numbers. But i seriously hope, we're not going to wait 2 years ...
...
So we waited 5 years, we can wait 6 months

He was talking about an old slide, not about today.

I dunno when they'll show up, but 6 months is optimistic, maybe 10-12 months. On the other hand, an AMD representative said in a BS-news interview that their 32 nm process is only 3 months behind Intel, although I find that hard to believe.

[FlanK3r]

6 months for some customers think. real launch im expect at 1H 2011 (April-Juni 2011)

[Hornet331]

On the other hand, an AMD representative said in a BS-news interview that their 32 nm process is only 3 months behind Intel, although I find that hard to believe.

So AMD is shipping and selling 32nm chips since april?

[savantu]

He was talking about an old slide, not about today.

I dunno when they'll show up, but 6 months is optimistic, maybe 10-12 months. On the other hand, an AMD representative said in a BS-news interview that their 32 nm process is only 3 months behind Intel, although I find that hard to believe.

Intel has been shipping millions of 32nm products since January. Add 3 months and you're in April. Maybe the representative said that on April 1 ?

[-Sweeper_]

You didn't factor any frequency gain. AMD is constantly comparing BD on energy efficiency and throughoutput with MC, doesn't say a word on IPC improvements.

A MC cpu has 12 integer cores and 12 floating point units; a BD cpu will have 16 integer cores ( a bit simpler than MC ) and 8 floating point units ( 2x de throughoutput of MC units when AVX is used - thus more complex FP)

If BD clocks 25% faster ( 2.7Ghz which isn't out of reach if 32nm works ) than you end up with no IPC improvement.

and theres a huge chance the clocks are higher, as magny cours runs at 1.9-2.3ghz

[Mats]

Well just because they CAN make 32 nm CPU's, it doesn't mean that they WILL do it right away..

But then again I see no reason for waiting.

Now that I had a look at it, it's over a year old.
http://www.brightsideofnews.com/news...-revealed.aspx

AMD was late with 65nm and introduced 45nm with a nine month delay. With 32nm we are reducing this on just a single quarter or three months.

[MrMojoZ]

Agreed, I hope Bulldozer is the same. One thing we can all agree on: the more competition the better it is for the consumer.

Hmm I'd rethink that statement. Smart people can all agree on: the more competition the better it is for the consumer. Some of the people posting in this thread want AMD out of business so that no one dares to compete with their precious Intel. I don't understand that logic, but here it is right in front of us.

[-Boris-]

Well just because they CAN make 32 nm CPU's, it doesn't mean that they WILL do it right away..

But then again I see no reason for waiting.

Now that I had a look at it, it's over a year old.
http://www.brightsideofnews.com/news...-revealed.aspx

AMD did good with the transition from 0.25µ to 0.18µ, but since then they have lagged behind. And since 0.13µ have they been saying that with the next transition they should be gaining on Intel. They haven't, so far.