RD890/SB800 - Hydra Engine + independant clocks per core?

[DstroyAllMnstrs]

Nice find.

There's only one thing, I hope RD890 is going to be great. Whether this new patent clock gen is going to be used or not, I dont know. If they use it, I really dont hope we've to wait 6 months again for a SB850 because SB800 turned out to fail just due to the clock gen.

But... I think AMD learned its lesson from SB600~SB750 pretty much, so I dont expect to see that happening anytime soon. But you never know, I just dont hope so. Im seriously planning to get a RD890 motherboard, but plese, let it work good

I agree - that delay really hurt AMD imo, esp. coming right off the heels of the TLB disaster.

No way I would have used the 600 series SB. I'll be getting onboard the Phenom II train soon unless the Opterons with HTT 3 come out at a really low price (doubtful).

This all sounds like good stuff coming. Now I hope they can execute flawlessly.

[rcofell]

Well, that patent proved somewhat insightful to read.

Basically what it's describing is a system for controlling multiple clock domains with those quadrature based clock generators (basically an adjustable frequency divider) and a single Phase Locked Loop to feed them with a reference quadrature clock pair (representable as a complex signal if you so wish ).
- (ie. system's reference clock -> main PLL -> main quadrature clock pair output [ideally two square waves 90deg out of phase] -> each domain's quadrature clock generator [controlled by a fairly simple state machine] -> clock domain's clock)

This is instead of doing something that involves adjusting multiple PLLs, so having a main PLL, plus one for each clock domain.
- (ie. system's reference clock -> PLL [managed by the Power Management Controller] -> adjusted main clock signal -> each clock domain's PLL [managed by the PMC] -> clock domain's clock)

Summed up, it essentially provides a finer grained approach to power management, while being pretty straight forward in implementation and more flexible than the prior. As instead of having to deal with adjusting the PLL dividers and the fairly significant wait-time while they lock back on, it's possible to just leave the main PLL alone and generate each clock domain's clock off of it independently with one of those quadrature clock generators, giving a much smaller lag time when switching power/frequency state.

Also, by using these clock generators it's possible to have a pretty good range of output frequencies; in the document it mentions such values as ref_value * .5, .75, 1, 1.25, 1.5, 1.75, 2, ..., 3, ..., 4, ...
What's also interesting is they have a diagram(Fig. 5) that shows an example system with a separate memory(DDR2) domain, along with some discussion about it in the document ([0044]-[0046]), which makes me wonder how adjustable the memory frequency can be, of course along with everything else. It definitely seems like a good system to handle the expanding number of clock domains that'll be present on a single chip in the future, like with fusion as the OP mentioned.


Hopefully I didn't go too in depth on things, spent long enough reading and trying to type all this out...
Now the question is when this will be implemented(has it already?) and how far we'll be able to tweak it, since the prospect of more adjustable parameters is always welcome

[Mechromancer]

Do we have any more evidence backing all of this up?

[Nedjo]

now if only web journalists would be so insightful as our members...

[Eson]

...then there wouldn't be as insightful members here anymore which this forum needs more of.

[Smartidiot89]

Well the Hydra engine seems to be true (first out on Intel x58 smackover), with Lucid Hydra having one of the main sponsors being: Intel

I can't find the article but it seems RD890 will support 4 x PCI-E 2.0 x16, unlike todays RD790(790FX) which can "only" support 4 x PCI-E 2.0 x8 or 2 x PCI-E 2.0 x16.

Iam definatly getting a AM3 platform when RD890 and SB800(SB850?) is out, atm DDR3 just seems to be a waste for AMD systems.

[roofsniper]

Well the Hydra engine seems to be true (first out on Intel x58 smackover), with Lucid Hydra having one of the main sponsors being: Intel

I can't find the article but it seems RD890 will support 4 x PCI-E 2.0 x16, unlike todays RD790(790FX) which can "only" support 4 x PCI-E 2.0 x8 or 2 x PCI-E 2.0 x16.

Iam definatly getting a AM3 platform when RD890 and SB800(SB850?) is out, atm DDR3 just seems to be a waste for AMD systems.

yep you are on the same boat as me. im only getting ddr3 once rd890 and sb800 come out. no reason to spend money to get only 1% off ddr3.

[the pharaoh]

Sounds like this is going to mark the "real" AM3 launch to me...forget these recycled 790FX/SB750 boards with DDR3 tacked-on we're seeing now.

New NB/SB combo with this fine clock control, Lucid Hydra and DDR3...now that's much more appealing.

[roofsniper]

Sounds like this is going to mark the "real" AM3 launch to me...forget these recycled 790FX/SB750 boards with DDR3 tacked-on we're seeing now.

New NB/SB combo with this fine clock control, Lucid Hydra and DDR3...now that's much more appealing.

yea amd never hits hard first they always release their first wave and then hit hard with the second. seems like that plan might not be working. rd890 + sb800 + 3.5ghz or better phenom II + ddr3 is where it is at. anyone got any more info on rd890? i haven't seen a thing.

[haylui]

this thread got virus?

[Smartidiot89]

yea amd never hits hard first they always release their first wave and then hit hard with the second. seems like that plan might not be working. rd890 + sb800 + 3.5ghz or better phenom II + ddr3 is where it is at. anyone got any more info on rd890? i haven't seen a thing.

http://www.fudzilla.com/index.php?op...11953&Itemid=1

Not much, but AMD has promised proper DDR3 support and we'll see what miracles the new southbridge can perform

[roofsniper]

yes but thats fud. they say its coming with sb850 which i always thought it was sb800 since there is no sb800 yet and i thought it had 4x16 pcie lanes and last time i checked its still set for q3.

[Smartidiot89]

yes but thats fud. they say its coming with sb850 which i always thought it was sb800 since there is no sb800 yet and i thought it had 4x16 pcie lanes and last time i checked its still set for q3.

First Q3, then AMD said Q2, now it will be late Q3/Q4.

Fudzilla is a reliable source, you just need to use your head and look past the bull they sometimes post :P

[w0mbat]

HYDRA is the codename for AMD 8-core opteron server cpus.

[Firestrider]

HYDRA is the codename for AMD 8-core opteron server cpus.

AMD kind of set themselves high with "Dragon". I can't think of a better creature besides "Human"

[informal]

HYDRA is the codename for AMD 8-core opteron server cpus.

Was hydra supposed to be a native 8 core shrank(32nm) Shanghai chip?Or was it planned to be a MCM of 2 45nm QCs?
I've done some "guesstimations" on my own .In the same space of the 6Mbs of L3,on the 32nm process,AMD can cram in ~20-24MBs of L3 provided the 0.49x scaling as in previous node transitions.Also the cores would be a lot smaller so the whole chip with 8 cores and 2MBs L2 per core(taking the smae die space as present 512KBs per core) and with that massive L3 would be the same die size or even smaller than Shanghai.Plus,they can do "smaller" six core part,a direct shrink of Istanbul(45nm) and cram the two shrank 6 core 32nm Istanbuls(~160-180mm2) on MCM. AMD will need to bring 32nm in Q2 of 2010 in order to fight Westmeres and Becktons,but it's not impossible.

[Nedjo]

HYDRA is the codename for AMD 8-core opteron server cpus.

there are sites that would love to spin their counters on this piece of news!

[Mechromancer]

The original plan for AMD's Hydra from back in May 2008: http://www.warepin.com/amd-hydra-octo-cores/

Looks like AMD finally realized that Nehalem is a serious competitor for the K10.5 CPUs. In this sense, after Deneb and Propus 45nm K10.5 Quad-cores AMD wants to change the process and improve the existing K10.5 cores.

The future process is called 45nm K10.5 Rev. D and it will bring the High K gating technology developed with IBM’s aid to 45nm SOI cores. As you have already intuited, the K10.5 Rev. C is the 45nm SOI process that AMD is supposed to use with the upcoming Deneb and Propus 45nm cores. AMD also came up with the Hydra codename for the Rev D cores, which seem to be the true response to Intel’s Nehalem.

The K10.5 Rev. D introduces 1MB L2 per core, which is twice as much as in current K10 CPUs, plus 6MB L3 cache memory. The Hydra CPUs are set to include at least eight cores, most likely coming in eight-core native design and not the recently announced MCM (Multi Chip Module).

Hydra CPUs are expected to easily hit +3GHz clock speeds in standard mode, but AMD will hopefully allow for fair overclocking potentioals.

That said, Nehalem will probably hold the crown for at least six to nine months before getting a real competitor. This is because AMD is rolling the Hydra CPUs sometime in mid 2009 or even later.

So it seems AMD's Octo Core was supposed to come with K10.5 Revision D silicon and challenge Nehalem in the 8-thread arena. Heh, woulda been nice. Hopefully we'll still get Rev. D AM3 quad cores that we can clock to high heaven this year.

[roofsniper]

hkmg and larger l2 caches might come this year but amd with 8 cores seems unlikely. isn't istanbul set for late q4?

[informal]

Yeah,the article is a bit wishfull thinking on teh author's part(seems like fudzilla piece hmm).
Anyhow,RevD is a 32nm thing IMO. It doesn't mean we get nothing with 45nm .We get an improved Deneb/Shanghai (process wise;we see this in chew's results already!) and we get a 6 core native beast in Q4! Not bad at all if you ask me .
Then sometime in 2010 we will have 32nm SOI shrink of Deneb/Shanghai line extended with native 6+ core parts(6/12 core MCM on servers). 2011 is a Bulldozer thing and maybe this is the true Hydra .

[demonkevy666]

oroochi is a bulldozer core that's the desktop part. that is 4 core slated for 2011.
this is wishfull thinking. If is dose trun true dose the mean AMd is play jump the tick and jump the tock lol
you forgot MCM montreal which could easiy be lowered voltage shanghai to 1.25 volts sitting in a MCM package at 3.0ghz would only use 150 watts.