Core Multiplexing technology???

[fhpchris]

I love AMD, it is too bad that they have no chance now

Intel is going to have the performance crown for a while if this comes true.

[erwinz]

Let's wait and see.. both intel and AMD have a secret.. hehehe the waiting is killing me.. :p

[metro.cl]

so current am2 cpus will work with anti ht?

[andL64]

so current am2 cpus will work with anti ht?

yes, like intel

and a bios update and new processor driver will unlock the feature

[metro.cl]

yes, like intel

and a bios update and new processor driver will unlock the feature

in this thead the say only conroe XE migh support this

thanks for the answer, i wont sell my am2 yet then

[[XC]Atomicpineapple]

Well I have a BIOS option on my Bad Axe for core multiplexing with an E6400, CPU is an ES tho.

[Cooper]

Well I have a BIOS option on my Bad Axe for core multiplexing with an E6400, CPU is an ES tho.

Screen ?

[Blacklash]

/Does happy dance

Can't wait for my Conroe!

[[XC]Atomicpineapple]

Cooper, rigs in bits atm for GFX card upgrade watercooling cleaning and a general tidy up! Will get it running on air later tho for a screenie.

**EDIT** Screenie as requested, appologies for poor pic quality, was taken from my camera phone.

[Cooper]

It`s good enough to read, thanks
But I guess this doesn`t do anything atm, right ?
Hmm...and what`s that SW Single Processor Mode is about ? Anyone have a clue ?

[[XC]Atomicpineapple]

According to FCGs post further up SW single processor mode disables 1 core totally.

[cpuz]

It`s good enough to read, thanks
But I guess this doesn`t do anything atm, right ?
Hmm...and what`s that SW Single Processor Mode is about ? Anyone have a clue ?

It disables one execution core, afaik.

I'm wondering how CMT manages several threads. I mean : when one logical CPU takes in charge several threads, the context switch overhead is not negligible. And HT for example allowed to handle two contextes for this reason. Still very fuzzy, anyway

[[XC]Atomicpineapple]

Ok, just tried a few things. Core multiplexing, when set to disabled, causes my PC to not boot. SW single CPU does indeed cause the PC to boot and use only 1 core. SW single core gave a slightly faster Pi time tho that may be an anomaly.

[Cooper]

Don`t think it`s a anomaly. L2 is shared, so you have all 2MB just for one core -> better result.
I wonder what core is disabled: 0 or 1 ? And is there a chance to control which to disable. By manufacturing one core might clock higher than another - would be great to have a tweak allowing to choose which core to disable (of course is there`re switches in both cores).

[freecableguy]

Cooper, see post #2 in this thread. I show pics....just disables core 1 and gives all 4MB/2MB cache to the functional core.

[Cooper]

Cooper, see post #2 in this thread. I show pics....just disables core 1 and gives all 4MB/2MB cache to the functional core.

Yeap. That was just what I`ve write, didn`t I ?
FCG perhaps any info on which core is disabled ?
I still haven`t seen any proof that one of the cores might be weaker, but don`t think it`s not a fact.

[freecableguy]

Always disables Core 1 (the secondary core).

[nn_step]

Ok, just tried a few things. Core multiplexing, when set to disabled, causes my PC to not boot. SW single CPU does indeed cause the PC to boot and use only 1 core. SW single core gave a slightly faster Pi time tho that may be an anomaly.

not even a second faster... looks like Multiplexing no work for that cpu...

[i||uSi0n^]

its quite normal coz it needs an updated cpu drivers for the windows for it to work...

i||uSi0n^

[[XC]Atomicpineapple]

nn_step, that wasnt multiplexing that was 1 core disabled and all the 2mb cache used by the 1 active core.

[ted3]

its quite normal coz it needs an updated cpu drivers for the windows for it to work...

I hope that driver is doing as little as possible other than enabling the feature, software emulation will always be inferior to real HW support, kind of like HT compared to preemptive multitasking. If this thing is anything like a Dual to Single SW Gateway its probably gonna suck.

[lawrywild]

Core multiplexing, when set to disabled, causes my PC to not boot.

Do you mean when Enabled

[grimREEFER]

amd's solution uses hypertransport while intel's solution uses shared L2 cache?
if this is true, isnt intel's solution going to be considerably better?

[caater]

amd's solution uses hypertransport while intel's solution uses shared L2 cache?
if this is true, isnt intel's solution going to be considerably better?

core family also have l1 to l1 direct link..

[nn_step]

amd's solution uses hypertransport while intel's solution uses shared L2 cache?
if this is true, isnt intel's solution going to be considerably better?

True, a shared L2 cache is superior to two processors connected Via Hypertransport link BUT such a design needs to be completely redesigned to add more processors. IN contrast all AMD needs to do is link and link. So for quick efficient upgrades AMD's is better BUT as a design for Performance ONLY a Shared L2 is about as good as it gets.