Not exciting news, it was obvious Intel would go this way. They only wanted to have a platform with higher margins not a platform that prices itself out of the market. For those higher margins Intel are prepared to make that platform more desirable, as last time (LGA1156) they made the mainstream platform too undesirable.
What I want is a clarification on PCI-E 3.0, the chipset says slides say 8x 2.0 lanes, but says nothing other than how it splits the lanes coming from the CPU (16x on two slots, or 8x on four slots).
Which is nice to know but all previous slides say SB-E is has a PCI-E 3.0 controller with 40 lanes and Intel is being vague about the subject. Does LGA2011 have both, or is it fully 2.0 now, and if so what happened?
Bookmarks