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Thread: Conroe 2.4Ghz on 965G mobo, brief test...

  1. #826
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    To compare Vic's latest results on Conroe to a 2.8 ghz dual core 1 MB cache Athlon64 X2 -- (with the same unofficial binary -- which I made myself)

    With the best compiled build (Pentium 4 build):

    Molecular Dynamics

    A64: 1872.68
    Cre: 2133.38

    Primordia

    A64: 1506.83
    Cre: 1365.85

    Cryptography

    A64: 1345.05
    Cre: 1065.59

    STREAM

    A64: 1512.55
    Cre: 1242.94

    Memory Benchmark

    A64: 1586.46
    Cre: 1465.20

    BLAS/FLOPs

    A64: 1449.17
    Cre: 1836.98

    MolDyn is a beast on Conroe -- but as you will see on multiple review websites, 64-bit mode is much faster in moldyn -- I can't wait to see a 64-bit result!

  2. #827
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    VictorWang, benchmark Comanche 4 Demo at 1024x768x32
    Opteron 170 @ 2.95GHz - 116fps
    can you run Comanche 4 Demo with Conroe ? Thanks
    Attached Images Attached Images

  3. #828
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    Why are you guys comparing a 2.8Ghz and 2.9Ghz AMd chips to a 2.4Ghz chip.....?


    Alex

  4. #829
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    i think people are starting to compare to high frequency chips cause they can't admit tha intel is and will be releasing a very good chip..

    i am not a fan from either company, what does the job, does the job.
    but seening some of these stats so far i think some amd fan bois, have to suck it up , and bow for the moment .

  5. #830
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    maybe it's so they know how much better the conroe is than the A64... yes, everyone knows it's superior clock for clock, but if we (the community as a whole) can say a conroe at 2.4ghz = a toledo at 2.9 or 3ghz, we can say it is xx% faster. isn't that the whole point of making comparisons?

  6. #831
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    Quote Originally Posted by AgonxOC
    Why are you guys comparing a 2.8Ghz and 2.9Ghz AMd chips to a 2.4Ghz chip.....?
    Why not?

    If a stock 2.4 ES Conroe, that's yet to be thoroughly sorted out, can win a few/lose a few, to a 2.8 A64-X2, that's saying quite a bit, IMHO.

    But seriously, I think it's just a case of the old street racer's adage of "run what ya' brung"!

    Yeah, not perfect "apples to apples", but hey, better than nothing at all!

    And let's face it: We are Overclockers!

    Now let's see what happens when the Conroe guys acquire the ability to start crankin' up the clocks/FSB's, & start doin' some OC'd benchies!

    *drools*

    Strat

    >edit<

    Wow, not trying to jump on you, man...looks like two quick posts came in before I was finshed composing mine!

    Oh well...

    >/edit<
    Last edited by Stratcat; 04-09-2006 at 07:18 PM.
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  7. #832
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    Quote Originally Posted by pik-ard v1.1
    maybe it's so they know how much better the conroe is than the A64... yes, everyone knows it's superior clock for clock, but if we (the community as a whole) can say a conroe at 2.4ghz = a toledo at 2.9 or 3ghz, we can say it is xx% faster. isn't that the whole point of making comparisons?
    Exactly

    The only reason I even posted sciencemark with my 170 @ 2.9GHz is because I had already done this test ages ago and wanted to show Conroe's superior performance, I did'nt set my 170 back to 2.4GHz because for one I just could'nt be bothered and secondly anyone with half a brain could extrapolate the performance clock to clock

    This AMD v Intel fanboy/girl talk is just soooooo childish and is not giving XS the respect it and the members deserve
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  8. #833
    great results..

  9. #834
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    This Conroe is just an A1 ES CPU... There are newer stepping already available...
    Victor, can you plz run HWiNFO32 (http://www.hwinfo.com) to check the machine?
    It should support Conroe and its thermal sensor too...
    Last edited by Mumak; 04-10-2006 at 02:16 AM.

  10. #835
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    Quote Originally Posted by Mumak
    This Conroe is just an A1 ES CPU... There are newer stepping already available...
    Victor, can you plz run HWiNFO32 (http://www.hwinfo.com) to check the machine?
    It should support Conroe and its thermal sensor too...
    where did you find A1 stepping?
    my friend told me it's an B0 stepping.

    A1 stepping cannot be used since lots of bugs
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  11. #836
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    Quote Originally Posted by VictorWang
    where did you find A1 stepping?
    my friend told me it's an B0 stepping.

    A1 stepping cannot be used since lots of bugs
    Trust me this one is A1...
    Last edited by Mumak; 04-10-2006 at 03:41 AM.

  12. #837
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    Hi Victor

    Update your Everest Systemanalyse 2.80.559 Beta :

    http://www.computerbase.de/downloads...lyse/?url=6170

    and look A1 or B0 ?

    thx

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  13. #838
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    Quote Originally Posted by Mumak
    Trust me this one is A1...
    And u know this because ... ?
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  14. #839
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    If you look at the CPUZ screenshots is says the stepping is 1. I don't know a lot about reading the steppings from software but it seems more likely to be an A1 to me.
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  15. #840
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    Quote Originally Posted by kyleslater
    If you look at the CPUZ screenshots is says the stepping is 1. I don't know a lot about reading the steppings from software but it seems more likely to be an A1 to me.
    you see the 1 , but what 1 ? maybe B1 !

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  16. #841
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    Quote Originally Posted by Cranox
    And u know this because ... ?
    Damn, because... I know. Can't tell more . Stop speculating
    Don't expect Everest to give you accurate result in this matter (Fiery consults this with me).

  17. #842
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    Quote Originally Posted by kyleslater
    If you look at the CPUZ screenshots is says the stepping is 1. I don't know a lot about reading the steppings from software but it seems more likely to be an A1 to me.
    Don't search for any scheme in assigning CPU Stepping numbers in CPUID - it's fully in hands of CPU vendors. If they decide Stepping = 1 to be C5/C6, then it's C5/C6

  18. #843
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    6F4 is the newer B0 rev.
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  19. #844
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    Quote Originally Posted by The Coolest
    6F4 is the newer B0 rev.
    Exactly

  20. #845
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    Quote Originally Posted by alpha0ne
    The only reason I even posted sciencemark with my 170 @ 2.9GHz is because I had already done this test ages ago and wanted to show Conroe's superior performance, I did'nt set my 170 back to 2.4GHz because for one I just could'nt be bothered and secondly anyone with half a brain could extrapolate the performance clock to clock
    Only to clarify. Have you noticed that Conroe 2.4 score with SM 2.0 *official* version is 1308 (neck to neck with X2 2.4)? and that the other score -with enormous moldyn score- is with *unofficial* and *special optimized binaries for Intel CPUs* made by redpriest?

  21. #846
    Guys,
    There's no bias here. Th e Intel optimized binary ran faster upon Opteorn as well. We, Alex and I, are looking for someone with a 64-bit Installation of Windows upon which we can test more accurately the true performance comparisons between Conroe and Opteron. These 32-bit binaries use x87 code which is legacy and not utilized in 64-bit. In 64-bit only SIMD arithmetic is utilized to perform FP operations. Moreoever, when SIMD is used we can build with the Intel compiler to enable vectorization and attempt to quantify how much faster Conroe is when those 128-bit engines in it's "Media Boost" unit are utilized. Opteron, P4 and pentium M have only 64-bit engines. Just look at the BLAS benchmark score.. there you see the beginnings of those 128-bit MEDIA processing units paying off.

    So.. any takers.. does someone have Windows 64-bit installed upon a Laptop. Alex and I can then continue our exploration of Conroe performance..

  22. #847
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    Tim,
    The version 9 of the intel compiler also allow optimization for AMD 64 as well. I'm not sure if their's new version of the compiler that have compilation flags for Macro op fusion that allows an extra instruction issue.

    The 128-bit SSE on Conroe will obviously benefit more than AMD 64 because two 64-bit SSE(x) intructions will now require one cycle unlike two in Presscott and Athlon 64. This is nobody's fault since Intel have concentrated more effort on making better CPU than crippling competitors performance on their compiler.

    You guys should be able to get a Conroe sample from Intel if you ask. Just write a request and give your website link as well as other link to websites using your benchmark.

    In the meantime, You can make an SSE/SSE2/SSE3 compiled binary for Victor to install Windows Server 2003 to test the power of Conroe. It will sure be interesting to see how that bad boy will do.

    Conroe/Woodcrest will surely be the new king for Molecular Dynamic Simulation developers. This will also reflect well on their SPEC results.
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  23. #848
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    Quote Originally Posted by agenda2005
    Tim,
    The version 9 of the intel compiler also allow optimization for AMD 64 as well. I'm not sure if their's new version of the compiler that have compilation flags for Macro op fusion that allows an extra instruction issue.

    The 128-bit SSE on Conroe will obviously benefit more than AMD 64 because two 64-bit SSE(x) intructions will now require one cycle unlike two in Presscott and Athlon 64. This is nobody's fault since Intel have concentrated more effort on making better CPU than crippling competitors performance on their compiler.

    You guys should be able to get a Conroe sample from Intel if you ask. Just write a request and give your website link as well as other link to websites using your benchmark.

    In the meantime, You can make an SSE/SSE2/SSE3 compiled binary for Victor to install Windows Server 2003 to test the power of Conroe. It will sure be interesting to see how that bad boy will do.

    Conroe/Woodcrest will surely be the new king for Molecular Dynamic Simulation developers. This will also reflect well on their SPEC results.
    Some of the folks here didn't read the link. It showed how Conroe processes 128Bit SIMDs in ONE CYCLE, not two as P4 and A64 does.

  24. #849
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    Quote Originally Posted by agenda2005

    The 128-bit SSE on Conroe will obviously benefit more than AMD 64 because two 64-bit SSE(x) intructions will now require one cycle unlike two in Presscott and Athlon 64. This is nobody's fault since Intel have concentrated more effort on making better CPU than crippling competitors performance on their compiler.
    Just for clarifications: SSE3 always has 128 bit instructions. On earlier platforms they might need more cycles to execute but the 128 bit instructions as such are present in any processor supporting SSE3.

    I don't think it is quite correct to say that two 64 bit SSE operations will now require half the time. This is only the case when ...
    • ... there are indeed independent units to compute. Doing two instructions at the same time requires that non depends on the outcome of the other. That is frequently not the case
    • .... and unless it is hand-coded assembly the compiler has to be sure about the previous fact. It can be nontrivial for the compiler to figure this out in a bulletproof way. If the compiler is not entirely sure it will default to be conservative
    • ... to be most effective the compiler has to be able to do out-of-order processing to scrap two 64 bit operations into one 128 bit one even if they are at different places in the source code. Prooving that this is safe is nontrivial, too, in particular in languages like C/C++ where there is a lot of aliasing going on

  25. #850
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    Quote Originally Posted by uOpt
    Just for clarifications: SSE3 always has 128 bit instructions. On earlier platforms they might need more cycles to execute but the 128 bit instructions as such are present in any processor supporting SSE3.

    I don't think it is quite correct to say that two 64 bit SSE operations will now require half the time. This is only the case when ...
    • Agreed, but that is usually the case for highly vecorized codes like MolDyn, BLAS and LINPACK. Two 64-bit SSE and SSE2 instructions can be fetch and decode in one cycle instead of one( As in A64 and Prescott) and the code scale according to the degree of vectorization.

      Quote Originally Posted by uOpt
    • ... there are indeed independent units to compute. Doing two instructions at the same time requires that non depends on the outcome of the other. That is frequently not the case
  26. That is where macro-op fusion comes into play. You can fuse two instructions together(for exapme, "compare" ) and perform the operation in one cycle.
    This will infact cut down branch mis-predictions that have plague prescott for a long time.

    Quote Originally Posted by uOpt
    [*] .... and unless it is hand-coded assembly the compiler has to be sure about the previous fact. It can be nontrivial for the compiler to figure this out in a bulletproof way. If the compiler is not entirely sure it will default to be conservative[/list]
    You can perform a Profile Guided Optimazation and let the compiler know the code structre a priori and then recompile for optimizations.
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