New Memory Tweaker for Intel Chipsets

**felix_w** · 10-06-2012, 11:24 AM

For me works almost ok...apart from frequency and Vcore...Vdimm, timings and timing set works ok, also all parts are recognized ok.

1090T M4A79 DLX and 2 sets of Blades 1150...

**dejanh** · 11-15-2012, 12:44 AM

Any plans to add SB-E support?

**myrddin669** · 03-17-2013, 02:14 PM

Apply is greyed on my Maximus III Formula, timings are shown correct,but can't change anything

**stasio** · 03-17-2013, 09:56 PM

Originally Posted by myrddin669

Apply is greyed on my Maximus III Formula, timings are shown correct,but can't change anything

You need CPU-Tweaker 1.4 :
http://www.plikus.pl/plik,cpu-tweaker-14,ivs.html

**caps_buster** · 09-15-2013, 03:13 PM

MemSet is a memory tweaker for:
(...)
-VIA KT266/333/400/600.

...is there any chance at all the MemSet tweaker will sometimes support the VIA P4M800 chipset? I can provide some testings there and the MSI PM8M3-V ( http://www.msi.com/product/mb/PM8M3-...div=CPUSupport ) mobo have a nice set of settings even in bios:

And MemSet works great on even old JetWay V266B mobo with KT266A chipset:

(yep, it wrongly identify the ram size as 1536MB, when there are only two DDR (the mobo supports even SDRAMs) slots and two 512MB modules are in them, totalling 1024MB - but that is minor detail - testing faster settings now, at 133MHz the rams should not need disabled interleaving or having so slow other timings

)

PS. Also in Soltek SL-KT600-R mobo ( http://www.motherboards.org/mobot/mo...ek/SL-KT600-R/ ) it is working just right, only not displaying the memory FSB:RAM ratio, as IIRC there is applied the FSB+33MHz VIA "thing" in the bios...

Kinda minor detail, I would say. VIA KT600 support works well also

But it is on my MSI PM8M3-V mobo (VIA P4M800 or even P4M800 Plus that support the DDR2 - dunno, but Everest it reports as the Plus version...) where I can't enable the 8 bank Interleave in bios (the mobo never boot anymore till jumper cleared the settings) and even I set the 1T commandrate, then it still show in all other sofrware 2T... but maybe that can be changed?

Perhaps w/o a crash also?

))

**caps_buster** · 10-04-2013, 08:04 AM

Carefull BUMP for P4M800 support?

**caps_buster** · 12-14-2013, 08:19 AM

Pretty please, with suggar on top, support the P4M800 chipset

**NEOAethyr** · 12-14-2013, 08:51 AM

Via huh....

I don't think that's intel's chip lol, believe it's actually nvidia's now but...

I don't know much about the north bridge, or at least I can't remember.
I think I do have something.
Most of the things I know about them are about latencies, and that there south bridges are pretty much identical across the line.
I can tell you the divider registers for the south bridge..., those I know for sure.

It really depends on what you're used to using for tweaks.
You can use dos and boot strap into windows, any windows... (not sure about ami's though, never tried one, award works, they have a standard going for there bootup).
Or you can use wpcredit/bar-edit.

I can't run either one right now honestly.
For some reason bar-edit is complain about a missing driver and of course wpcredit doesn't run in win x64.

I don't know if I updated these or not, they're dated 2006 from the last time I edited them apparently.

You'll have to figure out which one is for which chip though.
It's likely the id's will be different...
But you should beable to change the id's into anything you want, literally, I got the back door device id thingy listed I think.

1106B099.pcr

Code:

;[COMMENT]=George E. Breese, 11/2002, based on Orca's 11068598.PCR
[COMMENT]=Made by NEOAethyr ,info from Guruad, George Breese & VIA.
[MODEL]=VT8367 (KT333CE)
[VID]=1106:VIA
[DID]=B099:AGP bridge

[00:7]=Vendor ID
[00:6]=(Same As Above)
[00:5]=(Same As Above)
[00:4]=(Same As Above)
[00:3]=(Same As Above)
[00:2]=(Same As Above)
[00:1]=(Same As Above)
[00:0]=(Same As Above)

[01:7]=Vendor ID
[01:6]=(Same As Above)
[01:5]=(Same As Above)
[01:4]=(Same As Above)
[01:3]=(Same As Above)
[01:2]=(Same As Above)
[01:1]=(Same As Above)
[01:0]=(Same As Above)

[02:7]=Device ID
[02:6]=(Same As Above)
[02:5]=(Same As Above)
[02:4]=(Same As Above)
[02:3]=(Same As Above)
[02:2]=(Same As Above)
[02:1]=(Same As Above)
[02:0]=(Same As Above)

[03:7]=Device ID
[03:6]=(Same As Above)
[03:5]=(Same As Above)
[03:4]=(Same As Above)
[03:3]=(Same As Above)
[03:2]=(Same As Above)
[03:1]=(Same As Above)
[03:0]=(Same As Above)

[04:7]=Address / Data Stepping  1=Wait Cycles Enabled
[04:6]=Parity Error Response    0=Disabled 1=Enabled
[04:5]=VGA Palette Snoop        0=Disabled 1=Enabled
[04:4]=Mem Write&Invalidate CMD 0=Disabled 1=Enabled
[04:3]=Special Cycle Recognition0=Disabled 1=Enabled
[04:2]=Bus Mastering            0=Disabled 1=Enabled
[04:1]=Memory Access            0=Disabled 1=Enabled
[04:0]=I/O Access               0=Disabled 1=Enabled

[05:1]=Fast BackToBack Cycle    0=Same Only 1=Diff Allow
[05:0]=System Error Line (SERR#)0=Disabled 1=Enabled

[06:7]=Fast BackToBack Capable  0=No Support 1=Supported
[06:6]=User Definable Features  0=No Support 1=Supported
[06:5]=66MHz Capable            0=No Support 1=Supported
[06:4]=New Capability List      0=No Support 1=Supported

[07:7]=Detected Parity Error    0=None 1=Error
[07:6]=Signaled SystemError Line0=None 1=Error
[07:5]=Received Master Abort    0=None 1=Aborted
[07:4]=Received Target Abort    0=None 1=Aborted
[07:3]=Signaled Target Abort    0=None 1=Aborted
[07:2]=Device Select Timing     10=Slow 11=Unknown
[07:1]=01=Medium                00=Fast
[07:0]=Data Parity Error        0=None 1=Error Detected

[08:7]=Revision ID
[08:6]=(Same As Above)
[08:5]=(Same As Above)
[08:4]=(Same As Above)
[08:3]=(Same As Above)
[08:2]=(Same As Above)
[08:1]=(Same As Above)
[08:0]=(Same As Above)

[09:7]=Programming Interface
[09:6]=(Same As Above)
[09:5]=(Same As Above)
[09:4]=(Same As Above)
[09:3]=(Same As Above)
[09:2]=(Same As Above)
[09:1]=(Same As Above)
[09:0]=(Same As Above)

[0A:7]=Sub Class
[0A:6]=(Same As Above)
[0A:5]=(Same As Above)
[0A:4]=(Same As Above)
[0A:3]=(Same As Above)
[0A:2]=(Same As Above)
[0A:1]=(Same As Above)
[0A:0]=(Same As Above)

[0B:7]=Base Class
[0B:6]=(Same As Above)
[0B:5]=(Same As Above)
[0B:4]=(Same As Above)
[0B:3]=(Same As Above)
[0B:2]=(Same As Above)
[0B:1]=(Same As Above)
[0B:0]=(Same As Above)

[0C:7]=Cache Line Size
[0C:6]=(Same As Above)
[0C:5]=(Same As Above)
[0C:4]=(Same As Above)
[0C:3]=(Same As Above)
[0C:2]=(Same As Above)
[0C:1]=(Same As Above)
[0C:0]=(Same As Above)

[0D:7]=Latency
[0D:6]=(Same As Above)
[0D:5]=(Same As Above)
[0D:4]=(Same As Above)
[0D:3]=(Same As Above)

[0E:7]=Header Type
[0E:6]=(Same As Above)
[0E:5]=(Same As Above)
[0E:4]=(Same As Above)
[0E:3]=(Same As Above)
[0E:2]=(Same As Above)
[0E:1]=(Same As Above)
[0E:0]=(Same As Above)

[0F:7]=Built In Self Test       0=No Support 1=Supported
[0F:6]=Initialize               Built In Self Test
[0F:3]=Completion Status
[0F:2]=(Same As Above)
[0F:1]=(Same As Above)
[0F:0]=(Same As Above)

[18]=Primary Bus Number

[19]=Secondary Bus Number

[1A]=Subordinate Bus Number

[1B]=Secondary Latency Timer

[1C:7]=I/O Base Address
[1C:6]=(Same As Above)
[1C:5]=(Same As Above)
[1C:4]=(Same As Above)
[1C:3]=I/O Addressing Capability
[1C:2]=(Same As Above)
[1C:1]=(Same As Above)
[1C:0]=(Same As Above)

[1D:7]=I/O Limit Address
[1D:6]=(Same As Above)
[1D:5]=(Same As Above)
[1D:4]=(Same As Above)
[1D:3]=I/O Addressing Capability
[1D:2]=(Same As Above)
[1D:1]=(Same As Above)
[1D:0]=(Same As Above)

[1E]=Secondary Status

[1F]=Secondary Status

[20:7]=Memory Base Address
[20:6]=(Same As Above)
[20:5]=(Same As Above)
[20:4]=(Same As Above)

[21:7]=Memory Base Address
[21:6]=(Same As Above)
[21:5]=(Same As Above)
[21:4]=(Same As Above)
[21:3]=(Same As Above)
[21:2]=(Same As Above)
[21:1]=(Same As Above)
[21:0]=(Same As Above)

[22:7]=Memory Limit Address
[22:6]=(Same As Above)
[22:5]=(Same As Above)
[22:4]=(Same As Above)

[23:7]=Memory Limit Address
[23:6]=(Same As Above)
[23:5]=(Same As Above)
[23:4]=(Same As Above)
[23:3]=(Same As Above)
[23:2]=(Same As Above)
[23:1]=(Same As Above)
[23:0]=(Same As Above)

[24:7]=Prefetch Mem BaseAddress
[24:6]=(Same As Above)
[24:5]=(Same As Above)
[24:4]=(Same As Above)

[25:7]=Prefetch Mem BaseAddress
[25:6]=(Same As Above)
[25:5]=(Same As Above)
[25:4]=(Same As Above)
[25:3]=(Same As Above)
[25:2]=(Same As Above)
[25:1]=(Same As Above)
[25:0]=(Same As Above)

[26:7]=Prefetch Mem LimitAddress
[26:6]=(Same As Above)
[26:5]=(Same As Above)
[26:4]=(Same As Above)

[27:7]=Prefetch MemLimitAddress
[27:6]=(Same As Above)
[27:5]=(Same As Above)
[27:4]=(Same As Above)
[27:3]=(Same As Above)
[27:2]=(Same As Above)
[27:1]=(Same As Above)
[27:0]=(Same As Above)

[2C:7]=Sub Vendor ID
[2C:6]=(Same As Above)
[2C:5]=(Same As Above)
[2C:4]=(Same As Above)
[2C:3]=(Same As Above)
[2C:2]=(Same As Above)
[2C:1]=(Same As Above)
[2C:0]=(Same As Above)

[2D:7]=Sub Vendor ID
[2D:6]=(Same As Above)
[2D:5]=(Same As Above)
[2D:4]=(Same As Above)
[2D:3]=(Same As Above)
[2D:2]=(Same As Above)
[2D:1]=(Same As Above)
[2D:0]=(Same As Above)

[2E:7]=Sub Device ID
[2E:6]=(Same As Above)
[2E:5]=(Same As Above)
[2E:4]=(Same As Above)
[2E:3]=(Same As Above)
[2E:2]=(Same As Above)
[2E:1]=(Same As Above)
[2E:0]=(Same As Above)

[2F:7]=Sub Device ID
[2F:6]=(Same As Above)
[2F:5]=(Same As Above)
[2F:4]=(Same As Above)
[2F:3]=(Same As Above)
[2F:2]=(Same As Above)
[2F:1]=(Same As Above)
[2F:0]=(Same As Above)

[34]=Capability Pointer

[3E:3]=VGA Present On AGP
[3E:2]=Foward ISA I/O Addresses

[40:7]=CPU To AGP Post Write
[40:6]=CPU To AGP Dynamic Burst
[40:5]=CPU To AGP 1WS BurstWrite
[40:4]=AGP To DRAM Prefetching
[40:3]=CPU To AGP PostWrite Halt
[40:2]=MDA Present On AGP
[40:1]=AGP Master Read Caching
[40:0]=AGP Delay Transactions

[41:7]=Retry Status             1=Retry Occured
[41:6]=Retry Timeout Action     0=Don't Stop 1=Normal
[41:5]=Retry Count              10=16 11=64
[41:4]=01=4                     00=2
[41:3]=Clear & Continue Retry   0=Disabled 1=Enabled
[41:2]=CPU Backoff On AGP Retry 0=Disabled 1=Enabled

[42:7]=AGP RdPrefetch For EnhCmd0=Allways 1=OnlyForEnhCMD
[42:6]=AGP Master 1WS Write
[42:5]=AGP Master 1WS Read
[42:3]=AGP DelayedTransaction TO
[42:2]=PrefetchDisableForDelayTO
[42:0]=GenStopAccessCacheLineEnd

[43:7]=NB To AGP Time Slot
[43:6]=1111=240GCLKs
[43:5]=0010=32GCLKs
[43:4]=0001=16GCLKs             0000=Disabled
[43:3]=AGP Master Time Slot
[43:2]=1111=240GCLKs
[43:1]=0010=32GCLKs
[43:0]=0001=16GCLKs             0000=Disabled

[44:7]=Revision ID Writeable    0=Readonly 1=Read & Write
[44:5]=Power Management Rx34    0:Rx34=00  1:Rx34=80
[44:4]=Reflect Rx7-6 in Rx1F-1E 0=Disabled 1=Enabled
[44:3]=Back Door Value Rx83[2-1]
[44:2]=(Same As Above)
[44:1]=Back Door Value Rx82[5]
[44:0]=Back Door Register EnableFor AGP Device ID Rx47-46

[45:7]=Force Fast Write QW      Aligned
[45:6]=Merge Multible CPU Trans Into 1 FastWrBurstCycles
[45:5]=MergeMultible CPUWrCyclesInto Fast WrBurst Cycles
[45:4]=MergeMultible CPUWrCyclesInto Fast WrBurst Cycles
[45:2]=Fast Wr Burst 4T Max     No Slave Flow Control
[45:1]=Fast Write Back To Back
[45:0]=Fast Write Initial Block 1 Wait State

[46]=PTP Bridge Device ID

[47]=PTP Bridge Device ID

[80]=Capability ID

[81]=Next Pointer

[82]=Power Mgmt Capabilities

[83]=Power Mgmt Capabilities II

[84:1]=Power State              10=Unknown 11=D3 Hot
[84:0]=01=Unknown               00=D0

[85]=Power Mgmt Status

[86]=AGP Bridge Support Exts

[87]=Power Mgmt Data

11063099.pcr

Code:

[COMMENT]=Made by NEOAethyr ,info from Guruad, George Breese & VIA.
[MODEL]=VT8367 (KT333CE)
[VID]=1106:VIA
[DID]=3099:North Bridge

[00:7]=Vendor ID
[00:6]=(Same As Above)
[00:5]=(Same As Above)
[00:4]=(Same As Above)
[00:3]=(Same As Above)
[00:2]=(Same As Above)
[00:1]=(Same As Above)
[00:0]=(Same As Above)

[01:7]=Vendor ID
[01:6]=(Same As Above)
[01:5]=(Same As Above)
[01:4]=(Same As Above)
[01:3]=(Same As Above)
[01:2]=(Same As Above)
[01:1]=(Same As Above)
[01:0]=(Same As Above)

[02:7]=Device ID
[02:6]=(Same As Above)
[02:5]=(Same As Above)
[02:4]=(Same As Above)
[02:3]=(Same As Above)
[02:2]=(Same As Above)
[02:1]=(Same As Above)
[02:0]=(Same As Above)

[03:7]=Device ID
[03:6]=(Same As Above)
[03:5]=(Same As Above)
[03:4]=(Same As Above)
[03:3]=(Same As Above)
[03:2]=(Same As Above)
[03:1]=(Same As Above)
[03:0]=(Same As Above)

[04:7]=Address / Data Stepping  1=Wait Cycles Enabled
[04:6]=Parity Error Response    0=Disabled 1=Enabled
[04:5]=VGA Palette Snoop        0=Disabled 1=Enabled
[04:4]=Mem Write&Invalidate CMD 0=Disabled 1=Enabled
[04:3]=Special Cycle Recognition0=Disabled 1=Enabled
[04:2]=Bus Mastering            0=Disabled 1=Enabled
[04:1]=Memory Access            0=Disabled 1=Enabled
[04:0]=I/O Access               0=Disabled 1=Enabled

[05:1]=Fast BackToBack Cycle    0=Same Only 1=Diff Allow
[05:0]=System Error Line (SERR#)0=Disabled 1=Enabled

[06:7]=Fast BackToBack Capable  0=No Support 1=Supported
[06:6]=User Definable Features  0=No Support 1=Supported
[06:5]=66MHz Capable            0=No Support 1=Supported
[06:4]=New Capability List      0=No Support 1=Supported

[07:7]=Detected Parity Error    0=None 1=Error
[07:6]=Signaled SystemError Line0=None 1=Error
[07:5]=Received Master Abort    0=None 1=Aborted
[07:4]=Received Target Abort    0=None 1=Aborted
[07:3]=Signaled Target Abort    0=None 1=Aborted
[07:2]=Device Select Timing     10=Slow 11=Unknown
[07:1]=01=Medium                00=Fast
[07:0]=Data Parity Error        0=None 1=Error Detected

[08:7]=Revision ID
[08:6]=(Same As Above)
[08:5]=(Same As Above)
[08:4]=(Same As Above)
[08:3]=(Same As Above)
[08:2]=(Same As Above)
[08:1]=(Same As Above)
[08:0]=(Same As Above)

[09:7]=Programming Interface
[09:6]=(Same As Above)
[09:5]=(Same As Above)
[09:4]=(Same As Above)
[09:3]=(Same As Above)
[09:2]=(Same As Above)
[09:1]=(Same As Above)
[09:0]=(Same As Above)

[0A:7]=Sub Class
[0A:6]=(Same As Above)
[0A:5]=(Same As Above)
[0A:4]=(Same As Above)
[0A:3]=(Same As Above)
[0A:2]=(Same As Above)
[0A:1]=(Same As Above)
[0A:0]=(Same As Above)

[0B:7]=Base Class
[0B:6]=(Same As Above)
[0B:5]=(Same As Above)
[0B:4]=(Same As Above)
[0B:3]=(Same As Above)
[0B:2]=(Same As Above)
[0B:1]=(Same As Above)
[0B:0]=(Same As Above)

[0C:7]=Cache Line Size
[0C:6]=(Same As Above)
[0C:5]=(Same As Above)
[0C:4]=(Same As Above)
[0C:3]=(Same As Above)
[0C:2]=(Same As Above)
[0C:1]=(Same As Above)
[0C:0]=(Same As Above)

[0D:7]=Latency
[0D:6]=(Same As Above)
[0D:5]=(Same As Above)
[0D:4]=(Same As Above)
[0D:3]=(Same As Above)

[0E:7]=Header Type
[0E:6]=(Same As Above)
[0E:5]=(Same As Above)
[0E:4]=(Same As Above)
[0E:3]=(Same As Above)
[0E:2]=(Same As Above)
[0E:1]=(Same As Above)
[0E:0]=(Same As Above)

[0F:7]=Built In Self Test       0=No Support 1=Supported
[0F:6]=Initialize               Built In Self Test
[0F:3]=Completion Status
[0F:2]=(Same As Above)
[0F:1]=(Same As Above)
[0F:0]=(Same As Above)

[10:7]=AGP Aperture Base        (Offsets 10-13)
[10:3]=Unknown

[11:7]=AGP Aperture Base        (Offsets 10-13)

[12:7]=Lower Prog Base Addy(0-3)(7 6 5 4 3 2 1 0)(<-Bits)
[12:6]=(1 1 1 1 1 0 0 0)     8M (1 1 1 1 0 0 0 0)    16M
[12:5]=(1 1 1 0 0 0 0 0)    32M (1 1 0 0 0 0 0 0)    64M
[12:4]=(1 0 0 0 0 0 0 0)   128M (0 0 0 0 0 0 0 0)   256M

[13:7]=Upper Program BaseAddress
[13:6]=(Same As Above)
[13:5]=(Same As Above)
[13:4]=(Same As Above)
[13:3]=Lower Prog Base Addy(4-7)(7 6 5 4 3 2 1 0)(<-Bits)
[13:2]=(AGP Aperture Size->)
[13:1]=(Same As Above)          (1 1 1 1 1 1 1 1)     1M
[13:0]=(1 1 1 1 1 1 1 0)     2M (1 1 1 1 1 1 0 0)     4M

[2C:7]=Sub Vendor ID
[2C:6]=(Same As Above)
[2C:5]=(Same As Above)
[2C:4]=(Same As Above)
[2C:3]=(Same As Above)
[2C:2]=(Same As Above)
[2C:1]=(Same As Above)
[2C:0]=(Same As Above)

[2D:7]=Sub Vendor ID
[2D:6]=(Same As Above)
[2D:5]=(Same As Above)
[2D:4]=(Same As Above)
[2D:3]=(Same As Above)
[2D:2]=(Same As Above)
[2D:1]=(Same As Above)
[2D:0]=(Same As Above)

[2E:7]=Sub Device ID
[2E:6]=(Same As Above)
[2E:5]=(Same As Above)
[2E:4]=(Same As Above)
[2E:3]=(Same As Above)
[2E:2]=(Same As Above)
[2E:1]=(Same As Above)
[2E:0]=(Same As Above)

[2F:7]=Sub Device ID
[2F:6]=(Same As Above)
[2F:5]=(Same As Above)
[2F:4]=(Same As Above)
[2F:3]=(Same As Above)
[2F:2]=(Same As Above)
[2F:1]=(Same As Above)
[2F:0]=(Same As Above)

[34:7]=AGPCapability ListPointer
[34:6]=(Same As Above)
[34:5]=(Same As Above)
[34:4]=(Same As Above)
[34:3]=(Same As Above)
[34:2]=(Same As Above)
[34:1]=(Same As Above)
[34:0]=(Same As Above)

[35:7]=AGPCapability ListPointer
[35:6]=(Same As Above)
[35:5]=(Same As Above)
[35:4]=(Same As Above)
[35:3]=(Same As Above)
[35:2]=(Same As Above)
[35:1]=(Same As Above)
[35:0]=(Same As Above)

[36:7]=AGPCapability ListPointer
[36:6]=(Same As Above)
[36:5]=(Same As Above)
[36:4]=(Same As Above)
[36:3]=(Same As Above)
[36:2]=(Same As Above)
[36:1]=(Same As Above)
[36:0]=(Same As Above)

[37:7]=AGPCapability ListPointer
[37:6]=(Same As Above)
[37:5]=(Same As Above)
[37:4]=(Same As Above)
[37:3]=(Same As Above)
[37:2]=(Same As Above)
[37:1]=(Same As Above)
[37:0]=(Same As Above)

[40:7]=VLink Specification ID
[40:6]=(Same As Above)
[40:5]=(Same As Above)
[40:4]=(Same As Above)
[40:3]=(Same As Above)
[40:2]=(Same As Above)
[40:1]=(Same As Above)
[40:0]=(Same As Above)

[41:6]=NB 32Bit Bus Width?      0=Disabled 1=Enabled
[41:5]=NB 16Bit Bus Width       0=Disabled 1=Enabled
[41:4]=NB 8Bit Bus Width        0=Disabled 1=Enabled
[41:3]=NB 4X Data Rate          0=Disabled 1=Enabled
[41:2]=NB 2X Data Rate          0=Disabled 1=Enabled
[41:1]=NB 1X Data Rate?         0=Disabled 1=Enabled
[41:0]=NB 8X Data Rate          0=Disabled 1=Enabled

[42:7]=VLink I/O Req Depth      1101=14 1110=15 1111=16
[42:6]=1010=11 1011=12 1100=13  0111=8  1000=9  1001=10
[42:5]=0100=5  0101=6  0110=7   0001=2  0010=3  0011=4
[42:4]=0000=1
[42:3]=VLink Buffer Size
[42:2]=(Same As Above)
[42:1]=(Same As Above)
[42:0]=(Same As Above)

[43:7]=NorthBridge I/O Req Depth1101=8 1110=9 1111=10
[43:6]=1010=6 1011=7 1100=7     0111=6 1000=4 1001=5
[43:5]=0100=3 0101=4 0110=5     0001=1 0010=2 0011=3
[43:4]=0000=0

[44:7]=NB To CPU Buffer Size
[44:6]=(Same As Above)
[44:5]=(Same As Above)
[44:4]=(Same As Above)
[44:3]=NB To DRAM Buffer Size
[44:2]=(Same As Above)
[44:1]=(Same As Above)
[44:0]=(Same As Above)

[45:7]=SB To NB Normal Priority Rotation (X4 VClk's)
[45:6]=1010=32 1011=64 11XX=INF 0111=4  1000=8  1001=16
[45:5]=0101=1  0110=2
[45:4]=(Same As Above)
[45:3]=SB To NB High Priority   Rotation (X2 VClk's)
[45:2]=1010=32 1011=64 11XX=INF 0111=4  1000=8  1001=16
[45:1]=0101=1  0110=2
[45:0]=(Same As Above)

[46:7]=NB DnStream Priority     0=Normal 1=High
[46:6]=NB DnLink Priority       0=Normal 1=High
[46:5]=Combine StpGt To V Cmd's 10=3:1 11=4:1
[46:4]=00=1:1 01=2:1
[46:3]=VLink Master Access Order
[46:2]=(Same As Above)
[46:1]=(Same As Above?)
[46:0]=(Same As Above?)

[47:2]=VLink Auto Disconnect    0=Disabled 1=Enabled
[47:1]=VLink Auto Disc On Halt  0:Disabled 1=Enabled
[47:0]=VLink Auto Disc On StpGt 0:Disabled 1=Enabled

[48:6]=VLink 32Bit Bus Width?   0=Disabled 1=Enabled
[48:5]=VLink 16Bit Bus Width    0=Disabled 1=Enabled
[48:4]=VLink 8Bit Bus Width     0=Disabled 1=Enabled
[48:3]=VLink 4X Data Rate       0=Disabled 1=Enabled
[48:2]=VLink 2X Data Rate       0=Disabled 1=Enabled
[48:1]=VLink 1X Data Rate?      0=Disabled 1=Enabled
[48:0]=VLink 8X Data Rate       0=Disabled 1=Enabled

[49:6]=SB 32Bit Bus Width?      0=Disabled 1=Enabled
[49:5]=SB 16Bit Bus Width       0=Disabled 1=Enabled
[49:4]=SB 8Bit Bus Width        0=Disabled 1=Enabled
[49:3]=SB 4X Data Rate          0=Disabled 1=Enabled
[49:2]=SB 2X Data Rate          0=Disabled 1=Enabled
[49:1]=SB 1X Data Rate?         0=Disabled 1=Enabled
[49:0]=SB 8X Data Rate          0=Disabled 1=Enabled

[4A:7]=SB To LPC I/O Req Depth  1101=14 1110=15 1111=16
[4A:6]=1010=11 1011=12 1100=13  0111=8  1000=9  1001=10
[4A:5]=0100=5  0101=6  0110=7   0001=2  0010=3  0011=4
[4A:4]=0000=1
[4A:3]=SB To LPC Buffer Size
[4A:2]=(Same As Above)
[4A:1]=(Same As Above)
[4A:0]=(Same As Above)

[4B:7]=SouthBridge I/O Req Depth1101=8 1110=9 1111=10
[4B:6]=1010=6 1011=7 1100=7     0111=6 1000=4 1001=5
[4B:5]=0100=3 0101=4 0110=5     0001=1 0010=2 0011=3
[4B:4]=0000=0

[4C:7]=PCI To VLink Buffer Size
[4C:6]=(Same As Above)
[4C:5]=(Same As Above)
[4C:4]=(Same As Above)
[4C:3]=PCI To PCI Buffer Size
[4C:2]=(Same As Above)
[4C:1]=(Same As Above)
[4C:0]=(Same As Above)

[4D:7]=NB To CPU Normal PriorityRotation (X4 VClk's)
[4D:6]=1010=32 1011=64 11XX=INF 0111=4  1000=8  1001=16
[4D:5]=0101=1  0110=2
[4D:4]=(Same As Above)
[4D:3]=NB To CPU High Priority  Rotation (X2 VClk's)
[4D:2]=1010=32 1011=64 11XX=INF 0111=4  1000=8  1001=16
[4D:1]=0101=1  0110=2
[4D:0]=(Same As Above)

[4E:7]=CNR Priority             0=Normal 1=High
[4E:6]=Onboard LAN Priority     0=Normal 1=High
[4E:4]=Onboard USB Priority     0=Normal 1=High
[4E:2]=Onboard IDE Priority     0=Normal 1=High
[4E:1]=Onboard AC97 Priority    0=Normal 1=High
[4E:0]=PCI Priority             0=Normal 1=High

[4F:7]=SB UpStream Priority     0=Normal 1=High
[4F:6]=SB UpLink Priority       0=Normal 1=High
[4F:0]=DnLink Wait for UpLink WrFlush 0=Normal 1=Enable

[54:6]=FSB Multiplier           0=100MHz 1=133MHz
[54:5]=ROMSIP Cfg 1=Use ROMSIP  0=MA/SCASA/SWEA Straps
[54:4]=DRAM Burst Length        0=4 1=8

[55:7]=0WS BackToBack Write to  diff DDR Bank 0=Dis 1=Ena
[55:5]=DQS Input DLL Adjustment 0=Disabled 1=Enabled
[55:4]=DQS Output DLL Adjustment0=Disabled 1=Enabled
[55:3]=DQM Removal (Always do   4-burst RW) 0=Dis 1=Enabl
[55:2]=DQS Output               0=Disabled 1=Enabled
[55:1]=Auto Precharge for TLB RdorCPU WB 0=Disable 1=Enab
[55:0]=Write Recovery Time      0=1 1=2

[56:7]=Bank 6 Ending
[56:6]=(Same As Above)
[56:5]=(Same As Above)
[56:4]=(Same As Above)
[56:3]=(Same As Above)
[56:2]=(Same As Above)
[56:1]=(Same As Above)
[56:0]=(Same As Above)

[57:7]=Bank 7 Ending
[57:6]=(Same As Above)
[57:5]=(Same As Above)
[57:4]=(Same As Above)
[57:3]=(Same As Above)
[57:2]=(Same As Above)
[57:1]=(Same As Above)
[57:0]=(Same As Above)

[58:7]=Bank 1/0 MA Map Type     111=256Mbitx8 or x4 SDRAM
[58:6]=110=256Mbitx16 SDRAM     101=256Mbitx32 SDRAM
[58:5]=100=64/128Mbit SDRAM     000=16Mbit SDRAM
[58:4]=Bank 1/0 Command Rate    0=2 1=1
[58:3]=Bank 3/2 MA Map Type     111=256Mbitx8 or x4 SDRAM
[58:2]=110=256Mbitx16 SDRAM     101=256Mbitx32 SDRAM
[58:1]=100=64/128Mbit SDRAM     000=16Mbit SDRAM
[58:0]=Bank 3/2 Command Rate    0=2 1=1

[59:7]=Bank 5/4 MA Map Type     111=256Mbitx8 or x4 SDRAM
[59:6]=110=256Mbitx16 SDRAM     101=256Mbitx32 SDRAM
[59:5]=100=64/128Mbit SDRAM     000=16Mbit SDRAM
[59:4]=Bank 5/4 Command Rate    0=2 1=1
[59:3]=Bank 7/6 MA Map Type     111=256Mbitx8 or x4 SDRAM
[59:2]=110=256Mbitx16 SDRAM     101=256Mbitx32 SDRAM
[59:1]=100=64/128Mbit SDRAM     000=16Mbit SDRAM
[59:0]=Bank 7/6 Command Rate    0=2 1=1

[5A:7]=Bank 0 Ending
[5A:6]=(Same As Above)
[5A:5]=(Same As Above)
[5A:4]=(Same As Above)
[5A:3]=(Same As Above)
[5A:2]=(Same As Above)
[5A:1]=(Same As Above)
[5A:0]=(Same As Above)

[5B:7]=Bank 1 Ending
[5B:6]=(Same As Above)
[5B:5]=(Same As Above)
[5B:4]=(Same As Above)
[5B:3]=(Same As Above)
[5B:2]=(Same As Above)
[5B:1]=(Same As Above)
[5B:0]=(Same As Above)

[5C:7]=Bank 2 Ending
[5C:6]=(Same As Above)
[5C:5]=(Same As Above)
[5C:4]=(Same As Above)
[5C:3]=(Same As Above)
[5C:2]=(Same As Above)
[5C:1]=(Same As Above)
[5C:0]=(Same As Above)

[5D:7]=Bank 3 Ending
[5D:6]=(Same As Above)
[5D:5]=(Same As Above)
[5D:4]=(Same As Above)
[5D:3]=(Same As Above)
[5D:2]=(Same As Above)
[5D:1]=(Same As Above)
[5D:0]=(Same As Above)

[5E:7]=Bank 4 Ending
[5E:6]=(Same As Above)
[5E:5]=(Same As Above)
[5E:4]=(Same As Above)
[5E:3]=(Same As Above)
[5E:2]=(Same As Above)
[5E:1]=(Same As Above)
[5E:0]=(Same As Above)

[5F:7]=Bank 5 Ending
[5F:6]=(Same As Above)
[5F:5]=(Same As Above)
[5F:4]=(Same As Above)
[5F:3]=(Same As Above)
[5F:2]=(Same As Above)
[5F:1]=(Same As Above)
[5F:0]=(Same As Above)

[60:7]=RAM Type Bank 6/7        10=DDR SDRAM 11=EDO?
[60:6]=00=SDRAM     01=FPG?
[60:5]=RAM Type Bank 4/5        10=DDR SDRAM 11=EDO?
[60:4]=00=SDRAM     01=FPG?
[60:3]=RAM Type Bank 2/3        10=DDR SDRAM 11=EDO?
[60:2]=00=SDRAM     01=FPG?
[60:1]=RAM Type Bank 0/1        10=DDR SDRAM 11=EDO?
[60:0]=00=SDRAM     01=FPG?

;Shadow ROM Control
[61:7]=ROM Shadow CC000h-CFFFFh 10=Read Only 11=Read & Wr
[61:6]=01=Write Only            00=Not Shadowed
[61:5]=ROM Shadow C8000h-CBFFFh 10=Read Only 11=Read & Wr
[61:4]=01=Write Only            00=Not Shadowed
[61:3]=ROM Shadow C4000h-C7FFFh 10=Read Only 11=Read & Wr
[61:2]=01=Write Only            00=Not Shadowed
[61:1]=ROM Shadow C0000h-C3FFFh 10=Read Only 11=Read & Wr
[61:0]=01=Write Only            00=Not Shadowed

;Shadow ROM Control II
[62:7]=ROM Shadow DC000h-DFFFFh 10=Read Only 11=Read & Wr
[62:6]=01=Write Only            00=Not Shadowed
[62:5]=ROM Shadow D8000h-DBFFFh 10=Read Only 11=Read & Wr
[62:4]=01=Write Only            00=Not Shadowed
[62:3]=ROM Shadow D4000h-D7FFFh 10=Read Only 11=Read & Wr
[62:2]=01=Write Only            00=Not Shadowed
[62:1]=ROM Shadow D0000h-D3FFFh 10=Read Only 11=Read & Wr
[62:0]=01=Write Only            00=Not Shadowed

;Shadow ROM Control II
[63:7]=ROM Shadow E0000h-EFFFFh 10=Read Only 11=Read & Wr
[63:6]=01=Write Only            00=Not Shadowed
[63:5]=ROM Shadow F0000h-FFFFFh 10=Read Only 11=Read & Wr
[63:4]=01=Write Only            00=Not Shadowed
[63:3]=Memory Hole              10=15M-16M 11=14M-16M
[63:2]=01=512K-640K             00=NA
[63:1]=A,BK Direct SMRAM Access 0=Enabled 1=Disabled
[63:0]=A,BK DRAM Access         0=Disabled 1=Enabled

[64:7]=RAS Precharge Delay      0=2 1=3
[64:6]=Active To Precharge Delay0=6 1=7
[64:5]=CAS Latency              10=2.5T 11=3T?
[64:4]=01=2T                    00=1.5T?
[64:3]=DRAM Type                0=Standard 1=Registered
[64:2]=RAS To CAS Delay         0=2 1=3
[64:1]=Bank Interleave          10=4-way    11=Unknown
[64:0]=01=2-way                 00=Disabled

[65:7]=AGP Timer (X4 MCLKs)
[65:6]=(Same As Above)
[65:5]=(Same As Above)
[65:4]=(Same As Above)
[65:3]=CPU Timer (X4 MCLKs)
[65:2]=(Same As Above)
[65:1]=(Same As Above)
[65:0]=(Same As Above)

[66:7]=DDR-DQS Input Delay      0=Auto 1=Manual
[66:6]=DDR-DQS Output Delay     0=Auto 1=Manual
[66:5]=Arbitration Parking      10=AGP 11=Unknown
[66:4]=01=CPU                   00=Last Bus Owner
[66:3]=AGP Priority
[66:2]=(Same As Above)
[66:1]=(Same As Above)
[66:0]=(Same As Above)

[67:7]=DDR DQS Input Delay      Bits 0-7 Used On DDR
[67:6]=(Same As Above)
[67:5]=(Same As Above)
[67:4]=(Same As Above)
[67:3]=(Same As Above)
[67:2]=(Same As Above)
[67:1]=SDRAM MD Latch Delay     11=ExternalFeedback Clock
[67:0]=10=External Clock        0X=Internal Clock

[68:7]=DDR DQS Output Delay
[68:6]=(Same As Above)
[68:5]=(Same As Above)
[68:4]=(Same As Above)
[68:3]=(Same As Above)
[68:2]=(Same As Above)
[68:1]=(Same As Above)
[68:0]=(Same As Above)

[69:7]=DRAM Clock Multiplier    10=3X 11=Auto (By SPD)
[69:6]=01=5X                    00=4X
[69:5]=DRAM Queue Depth         10=2 11=3
[69:4]=01=4                     00=8
[69:3]=DRAM Page Length         10=8       11=Unknown
[69:2]=00=Unknown 01=4
[69:1]=DRAM ECC                 0=Disabled 1=Enabled
[69:0]=DRAM Multiple Page Mode  0=Disabled 1=Enabled

[6A:7]=DRAM Refresh Counter
[6A:6]=(Same As Above)
[6A:5]=(Same As Above)
[6A:4]=(Same As Above)
[6A:3]=(Same As Above)
[6A:2]=(Same As Above)
[6A:1]=(Same As Above)
[6A:0]=(Same As Above)

[6B:7]=Fast Read To WriteTA(MA?)0=Disabled 1=Enabled
[6B:6]=Page Act When Cross Bank 0=Disabled 1=Enabled
[6B:5]=RAMBurstRefresh(FastTLB?)0=Disable 1=Enabled
[6B:4]=CKE Configuration        0=6 Bank 1=8 Bank
[6B:3]=Swap CA22/CA14           0=Disable 1=Enabled
[6B:2]=SDRAM Operation Mode     100=CBR Cycle 101-111=?
[6B:1]=011=MSR Enabled          010=All Banks Precharge
[6B:0]=001=NOP Command Enabled  000=Normal

[6C:7]=SDRAM A Drive            10=High   11=Highest
[6C:6]=01=Lower                 00=Lowest
[6C:5]=SDRAM B Drive            10=High   11=Highest
[6C:4]=01=Lower                 00=Lowest
[6C:3]=DDR DQS Drive            10=High   11=Highest
[6C:2]=01=Lower                 00=Lowest
[6C:1]=MD-MECC-CAS-CKE Early ClkSelect
[6C:0]=10=Early  11=Earliest    00=Latest 01=Late

[6D:7]=SCMD-MA Early Clk Select 10=Early  11=Earliest
[6D:6]=01=Late                  00=Latest
[6D:5]=DQM Drive                10=High   11=Highest
[6D:4]=01=Lower                 00=Lowest
[6D:3]=RAS# Drive               10=High   11=Highest
[6D:2]=01=Lower                 00=Lowest
[6D:1]=MD-MECC Drive            10=High   11=Highest
[6D:0]=01=Lower                 00=Lowest

[6E:7]=ECC / ECMode Select      1=Chk,Repair and Correct
[6E:6]=Read Modify Wr For PartWr
[6E:5]=System Parity Line DIMM010=Disabled 1=Enabled
[6E:4]=System Parity Line DIMM230=Disabled 1=Enabled
[6E:3]=ECC/EC Bank 7/6 (DIMM 3) 0=Disable   1=Enable
[6E:2]=ECC/EC Bank 5/4 (DIMM 2) 0=Disable   1=Enable
[6E:1]=ECC/EC Bank 3/2 (DIMM 1) 0=Disable   1=Enable
[6E:0]=ECC/EC Bank 1/0 (DIMM 0) 0=Disable   1=Enable

[6F:7]=Multi-Bit Error Detected 0=None 1=Error
[6F:6]=Multi-Bit Error DRAM 
[6F:5]=001-111=Error
[6F:4]=0=None
[6F:3]=Single-Bit Error Detected0=None 1=Error
[6F:2]=Single-Bit Error DRAM
[6F:1]=001-111=Error
[6F:0]=0=None

[70:7]=CPU to PCI Post Write    0=Disabled 1=Enabled
[70:6]=PCI To DRAM Post Write   0=Disabled 1=Enabled
[70:5]=PCI To DRAM Prefetch     11=Never
[70:4]=10=Only For Enhance Cmd  00=Always 01=Never
[70:3]=Delayed CPU To PCI Write 0=Normal 1=Delayed
[70:2]=PCI Master Read Caching  0=Disabled 1=Enabled
[70:1]=PCI Delayed Transactions 0=Disabled 1=Enabled
[70:0]=Slave Dev Stopped Idle   0=Normal 1=Delayed

[71:7]=Dynamic Bursting         0=Disabled 1=Enabled
[71:6]=Byte Merging             0=Disabled 1=Enabled
[71:4]=PCI I/O Cycle Post Writes0=Disabled 1=Enabled
[71:3]=PCI Bursting             0=Disabled 1=Enabled
[71:2]=PCI Fast Back To Back Wr 0=Disabled 1=Enabled
[71:1]=Quick Frame Generation   0=Disabled 1=Enabled
[71:0]=PCI Wait State           0=0Ws? 1=1Ws

[72:7]=Retry Status             0=No 1=Yes
[72:6]=Retry Timeout Action     0=Retry 1=Flush
[72:5]=Retry Count And Backoff  10=4X 11=64X
[72:4]=01=16X                   00=2X
[72:3]=Clear Fail Data And Retry0=Flush 1=Pop Bad Data
[72:2]=PCI Read Retry Fail      0=Normal 1=Backoff CPU
[72:1]=Frame# Generation Timing 0=Normal 1=-1T
[72:0]=CPU Read PCI Slave Timing0=Normal 1=-1T

[73:6]=PCI Master Wr Wait State 0=0Ws 1=1Ws
[73:5]=PCI Master Rd Wait State 0=0Ws 1=1Ws
[73:4]=WSC#                     0=Disabled 1=Enabled
[73:3]=Assert STOP# For PCI WrTO0=Disabled 1=Enabled
[73:2]=Assert STOP# For PCI RdTO0=Disabled 1=Enabled
[73:1]=LOCK# Function           0=Disabled 1=Enabled
[73:0]=PCI Master Broken Timer  0=Disabled 1=Enabled

[74:7]=PCI Read Prefetching     0=Always 1=Only For E Cmd
[74:4]=Dummy Request
[74:3]=PCI Delay Transaction TO 0=Disabled 1=Enabled
[74:2]=Backoff CPU Immediately  0=Disabled 1=Enabled
[74:1]=AGP Latency Reset Timing 10=Rising Edge Reset 11=?
[74:0]=01=Falling Edge Reset    00=AGP Card Resets Timer

[75:7]=Arbitration Policy       0=PCI Has Priority 1=Fair
[75:6]=Arbitration Mode         0=Req Based 1=Frame Based
[75:5]=CPU On PCIBus LatencyBit2
[75:4]=CPU On PCIBus LatencyBit1
[75:3]=PCI Master Bus Time Out  0000=Disabled
[75:2]=0001=1x32 PCIClk's       0010=2x32 PCIClk's
[75:1]=0011=3x32 PCIClk's       0100=4x32 PCIClk's
[75:0]=0111=7x32 PCIClk's       1111=15x32 PCIClk's

[76:7]=CTP Post Wr Retry Failed 0=Retry 1=GoToArbitration
[76:6]=CPU On PCIBus LatencyBit0
[76:5]=Master Priority Rotation 10=2 PCI-CPU 11=3 PCI-CPU
[76:4]=01=CPU Access after 1 PCI00=No CTP If PCI In Use
[76:3]=REQ# To REQ4# Mapping    10=REQ1# 11=REQ2#
[76:2]=01=REQ0#                 00=REQ4#
[76:1]=CPU QW Or PCI Slave Read 0=Normal 1=Allow Back Off
[76:0]=REQ4# Priority           0=Normal 1=High

[77:7]=Chip Test Mode
[77:6]=(Same As Above)
[77:5]=(Same As Above)
[77:4]=(Same As Above)
[77:3]=(Same As Above)
[77:2]=(Same As Above)
[77:1]=(Same As Above)
[77:0]=(Same As Above)

[78:7]=I/O Port 22 Access       0=CPU Passes To PCI 1=CPU
[78:6]=Suspend Refresh Type     0=CBR 1=Self Refresh
[78:4]=Dynamic Clock Control    0=Disabled 1=Enabled
[78:2]=GSTOP# Assertion         0=Disabled 1=Enabled
[78:0]=MEM Clock (CKE) Function 0=Disabled 1=Enabled

[79:2]=Indicate SIO Req For DRAM0=Disabled 1=Enabled
[79:0]=2T Snoop Wr Inval RdCache0=Disabled 1=Enabled

[7A:7]=ArbConsecutiveFrameAccess0=No Timeout 1=TimeOut
[7A:4]=InVal CPUToPCI-AGPRdCache0=Disabled 1=Enabled
[7A:3]=Background PCI To PCI Wr 0=Disabled 1=Enabled
[7A:0]=PCI Force Timeout Timer  0=Disabled 1=Enabled 

[7B:1]=PCI Access               0=Tail 1=Head

[7E:7]=DLL/PLL Test Mode
[7E:6]=(Same As Above)
[7E:5]=(Same As Above)
[7E:4]=(Same As Above)
[7E:3]=(Same As Above)
[7E:2]=(Same As Above)
[7E:1]=(Same As Above)
[7E:0]=(Same As Above)

[7F:7]=DLL/PLL Test Mode II
[7F:6]=(Same As Above)
[7F:5]=(Same As Above)
[7F:4]=(Same As Above)
[7F:3]=(Same As Above)
[7F:2]=(Same As Above)
[7F:1]=(Same As Above)
[7F:0]=(Same As Above)

[80:7]=Flush Page TLB           0=Disabled 1=Enabled
[80:3]=PCI Address Translation  0=Disabled 1=Enabled
[80:2]=AGP Address Translation  0=Disabled 1=Enabled
[80:1]=CPU Address Translation  0=Disabled 1=Enabled
[80:0]=AGP Address Translation  0=Disabled 1=Enabled

[81:7]=Page TLB Bank Test Data 1(AND Function)
[81:6]=Page TLB Bank Test Data 0(OR Function)
[81:5]=Page LRU Parity
[81:4]=GART TLB LRU Parity
[81:3]=GART TLB Test Data 1     (AND Fuction)
[81:2]=GART TLB Test Data 0     (OR Fuction)
[81:1]=Page TLB Test Data 1     (AND Fuction)
[81:0]=Page TLB Test Data 0     (OR Fuction)

[84:7]=Graphics Aperture Size   00000000 256Megs
[84:6]=10000000 128Megs
[84:5]=11000000  64Megs
[84:4]=11100000  32Megs
[84:3]=11110000  16Megs
[84:2]=11111000   8Megs
[84:1]=11111100   4Megs
[84:0]=11111110   2Megs         11111111   1Megs

[88:2]=One Cycle TLB Flush      0=4 Cycle 1=1 Cycle
[88:1]=Graphics Aperture        0=Disabled 1=Enabled

[89:7]=Graphics Aperture        Translation Table
[89:6]=(Same As Above)
[89:5]=(Same As Above)
[89:4]=(Same As Above)

[8A:7]=Graphics Aperture        Translation Table
[8A:6]=(Same As Above)
[8A:5]=(Same As Above)
[8A:4]=(Same As Above)
[8A:3]=(Same As Above)
[8A:2]=(Same As Above)
[8A:1]=(Same As Above)
[8A:0]=(Same As Above)

[8B:7]=Graphics Aperture        Translation Table
[8B:6]=(Same As Above)
[8B:5]=(Same As Above)
[8B:4]=(Same As Above)
[8B:3]=(Same As Above)
[8B:2]=(Same As Above)
[8B:1]=(Same As Above)
[8B:0]=(Same As Above)

;S2k Timing Control
[90:7]=Disable ROM Table        0=BIOS 1=Read From Reg's
[90:5]=ReadDataDelay|SDCOutDelay
[90:4]=(Same As Above)
[90:3]=WriteDataDelay|SDCInDelay
[90:2]=(Same As Above)
[90:1]=(Same As Above)
[90:0]=(Same As Above)

;S2K Timing Control II
[91:7]=NB DataRcvrMux Init Count(Dinit)
[91:6]=(Same As Above)
[91:5]=NB AddrRcvrMux Init Count(Ainit)
[91:4]=(same as above)
[91:2]=CPU Data&AddrMux PreCount(MuxPreLd)
[91:1]=(Same As Above)
[91:0]=(Same As Above)

;S2K Timing Control III
[92:7]=Disc when STPGNT Detected0=Disabled 1=Enabled
[92:6]=Write to Read Delay
[92:5]=Read to Write Delay
[92:4]=(Same As Above)
[92:3]=1ns Skew Between -       Even Odd Clock Group
[92:2]=Wr Data Delay From SYSDC To CPU Output (WrDataDly)
[92:1]=(Same As Above)
[92:0]=(Same As Above)

[93:7]=MaxContigProbeSysDC
[93:6]=(Same As Above)
[93:5]=MaxContigReadSysDC
[93:4]=(Same As Above)
[93:3]=(Same As Above)
[93:2]=MaxContigWriteSysDC
[93:1]=(Same As Above)
[93:0]=(Same As Above)

[94:7]=SDRAM SelfRefresh @ Disc 0=Disabled 1=Enabled
[94:6]=PCI Rd C Prb Nxt Tg St T10=Disabled 1=Enabled
[94:5]=S2K Data Input Buffer    0=Disabled 1=Enabled
[94:4]=S2K Data Output Timing   0=1T Setup 1=1/2T Setup
[94:3]=DRAM Speculative Read    0=Disabled 1=Enabled
[94:2]=PCI Master Pipelining Req0=Disabled 1=Enabled
[94:1]=PCIToCPU CPUToPCI Concur 0=Disabled 1=Enabled
[94:0]=Fast ReadToWrite TA      0=disable  1=enabled

[95:7]=FWDVLD/PSQHPTR concurr'y 0=compatible 1=not
[95:6]=RHOCTW
[95:5]=PMW Address Compare      0=compat 1=cmp ad q w/PMW
[95:4]=Write Policy CPU to RAM  0=FIFO>2 or idle  1=disa
[95:3]=PMR Cycle Control        0=Stall if MWQ full
[95:2]=FID Command Detect       0=disable  1=enable
[95:1]=HALT Command Detect      0=disable  1=enable

[96:7]=Mem Wrt Que Timer funct  0=disable  1=enable
[96:6]=Mem Wrt Que Trigger      0=dat rdy C2M 1=FIFO use
[96:5]=Mem Wrt Que High Bound   in units of 4QW/req#
[96:4]=(Same as above)
[96:3]=(Same as above)
[96:2]=Mem Wrt Que High Bound   in units of 4QW/req#
[96:1]=(Same as above)
[96:0]=(Same as above)

[97:7]=CPU Clock Division       0000=11 0001=12
[97:6]=0010=5  0011=6  0100=7   0101=8  0110=9 0111=10
[97:5]=1000=3  1001=4
[97:4]=(same as above)
[97:3]=Add 0.5 to above CPU Clk Divisor
[97:2]=S2K Drive Strength       0=by register 1=auto comp
[97:1]=Address Out Decode       0=Normal 1=Fast
[97:0]=S2K Compensation Circuit 0=always 1=ena on disconn

[98:7]=S2K Pullup Drive Strength
[98:6]=(Same As Above)
[98:5]=(Same As Above)
[98:4]=(Same As Above)
[98:3]=S2K Pulldown Drv Strength
[98:2]=(Same As Above)
[98:1]=(Same As Above)
[98:0]=(Same As Above)

[99:7]=S2K Pullup Auto          Compensation Result
[99:6]=(Same As Above)
[99:5]=(Same As Above)
[99:4]=(Same As Above)
[99:3]=S2K Pulldown Auto        Compensation Result
[99:2]=(Same As Above)
[99:1]=(Same As Above)
[99:0]=(Same As Above)

[9A:7]=S2K Edge DQ Mode         0=Central DQ 1=Edge DQ
[9A:6]=S2K Strobe Delay (EdgeDQ)0000000=auto
[9A:5]=(Same As Above)
[9A:4]=(Same As Above)
[9A:3]=(Same As Above)
[9A:2]=(Same As Above)
[9A:1]=(Same As Above)
[9A:0]=(Same As Above)

[9B]=S2K Strobe DLL Delay       Counter (Auto)

[9C:7]=S2K Compensation Circuit Trigger
[9C:6]=DLL AutoDetect
[9C:5]=Delay Compensation       Counter Control
[9C:4]=S2K Pad AC Coupling to   VREF Signal in Address
[9C:3]=Data Output Clock
[9C:2]=S2K Pad Slew Rate Ctrl
[9C:1]=111=Strongest
[9C:0]=000=Weakest

[9D:7]=S2K Strobe Output Drive  P Control
[9D:6]=(Same As Above)
[9D:5]=(Same As Above)
[9D:4]=(Same As Above)
[9D:3]=S2K Strobe Output Drive  N Control
[9D:2]=(Same As Above)
[9D:1]=(Same As Above)
[9D:0]=(Same As Above)

[9E:7]=Unknown
[9E:6]=(Same As Above)
[9E:5]=(Same As Above)
[9E:4]=(Same As Above)

[A0:7]=AGP ID
[A0:6]=(Same As Above)
[A0:5]=(Same As Above)
[A0:4]=(Same As Above)
[A0:3]=(Same As Above)
[A0:2]=(Same As Above)
[A0:1]=(Same As Above)
[A0:0]=(Same As Above)

[A1:7]=Pointer to Next Item
[A1:6]=(Same As Above)
[A1:5]=(Same As Above)
[A1:4]=(Same As Above)
[A1:3]=(Same As Above)
[A1:2]=(Same As Above)
[A1:1]=(Same As Above)
[A1:0]=(Same As Above)

[A2:7]=Major Specification Rev
[A2:6]=(Same As Above)
[A2:5]=(Same As Above)
[A2:4]=(Same As Above)
[A2:3]=Minor Specification Rev
[A2:2]=(Same As Above)
[A2:1]=(Same As Above)
[A2:0]=(Same As Above)

[A4:5]=4G Addressing Supported
[A4:4]=Fast Write's Supported
[A4:3]=8X Data Rate Supported?
[A4:2]=4X Data Rate Supported
[A4:1]=2X Data Rate Supported
[A4:0]=1X Data Rate Supported

[A5:3]=Unknown
[A5:1]=AGP SideBanding Supported

[A7:7]=AGP Request Depth
[A7:6]=(Same As Above)
[A7:5]=(Same As Above)
[A7:4]=(Same As Above)
[A7:3]=(Same As Above)
[A7:3]=(Same As Above)
[A7:2]=(Same As Above)
[A7:1]=(Same As Above)
[A7:0]=(Same As Above)

[A8:5]=AGP 4G Adressing         0=Disabled 1=Enabled
[A8:4]=AGP Fast Write's         0=Disabled 1=Enabled
[A8:3]=AGP 8X Data Rate?        0=Disabled 1=Enabled
[A8:2]=AGP 4X Data Rate         0=Disabled 1=Enabled
[A8:1]=AGP 2X Data Rate         0=Disabled 1=Enabled
[A8:0]=AGP 1X Data Rate         0=Disabled 1=Enabled

[A9:1]=SideBand Addressing      0=Disabled 1=Enabled
[A9:0]=AGP Enable               0=Disabled 1=Enabled

[AB:7]=AGP RequestDepth FromCard
[AB:6]=(Same As Above)
[AB:5]=(Same As Above)
[AB:4]=(Same As Above)
[AB:3]=(Same As Above)
[AB:2]=(Same As Above)
[AB:1]=(Same As Above)
[AB:0]=(Same As Above)

[AC:7]=Unknown
[AC:6]=CPUStall On AGP FIFO GART0=Disabled 1=Enabled
[AC:5]=AGP Read Snoop DRAM P-W-B0=Disabled 1=Enabled
[AC:4]=GREQ#Priority WhenAGPPark0=Normal 1=High
[AC:3]=AGP 2X Data Rate Support 0=Disabled 1=Enabled
[AC:2]=LPR In Order Access      0=Not 1=Executed
[AC:1]=AGP Arbitration Parking  0=Disabled 1=Enabled
[AC:0]=AGPToPCI CPUToPCI TACycle0=2T or 3T  1=1T

[AD:6]=AGPData/StrobeInputBuffer0=Disabled 1=Enabled
[AD:5]=Hold Last GD Output Data 0=Disabled 1=Enabled
[AD:4]=1st/Last Ready Of DRAM   0=Last 1=1st
[AD:3]=AGP Data Phase Latency
[AD:2]=(Same As Above)
[AD:1]=(Same As Above)
[AD:0]=(Same As Above)

[AE:5]=AGP 4GBAddressing Support0=Disabled 1=Enabled
[AE:4]=AGP FastWrite's Support  0=Disabled 1=Enabled
[AE:2]=AGP 4X Data Rate Support 0=Disabled 1=Enabled

[AF:7]=AGP Strobe Output Drive  Strength N Control
[AF:6]=(Same As Above)
[AF:5]=(Same As Above)
[AF:4]=(Same As Above)
[AF:3]=AGP Strobe Output Drive  Strength P Control
[AF:2]=(Same As Above)
[AF:1]=(Same As Above)
[AF:0]=(Same As Above)

[B0:7]=AGP 4x Strobe VREF Ctrl  0=STB#/v-v  1=AGPREF
[B0:6]=AGP 4x Strobe & GD Pad   0=C-Circuit 1=By Reg B1
[B0:5]=AGP Compensation Circuit N Control Output
[B0:4]=(Same As Above)
[B0:3]=(Same As Above)
[B0:2]=AGP Compensation Circuit P Control Output
[B0:1]=(Same As Above)
[B0:0]=(Same As Above)

[B1:7]=AGP Output Buffer Drive  Strength N Ctrl
[B1:6]=(Same As Above)
[B1:5]=(Same As Above)
[B1:4]=(Same As Above)
[B1:3]=AGP Output Buffer Drive  Strength P Ctrl
[B1:2]=(Same As Above)
[B1:1]=(Same As Above)
[B1:0]=(Same As Above)

[B2:7]=GD/GBE/GDS,SBA/SBSControl0=No Cap 1=Capped
[B2:5]=S2K Slew Rate Control    0=Enabled 1=Disabled
[B2:4]=GD[31:16] Staggered Delay0=none      1=1ns
[B2:3]=AGP Preamble Control     0=Disbled 1=Enabled
[B2:1]=AGP Voltage              0=1.5V      1=3.3V
[B2:0]=GDS Output Delay         0=none      1=0.4ns

[B4:7]=NB AutoCompensation Value
[B4:6]=(Same As Above)
[B4:5]=NB PullUp Compensation   0=Auto 1=Manual
[B4:4]=NB PullDn Compensation   0=Auto 1=Manual
[B4:3]=NB PullUp Compensation
[B4:2]=(Same As Above)
[B4:1]=NB PullDn Compensation
[B4:0]=(Same As Above)

[B5:7]=VLink Strobe Pullup      Manual Setting
[B5:6]=(same as above)
[B5:5]=VLink Strobe Pulldown    Manual Setting
[B5:4]=(same as above)
[B5:0]=VLink Slew Rate Control  0=Disabled 1=Enabled

[B8:7]=SB Autocompensation Value
[B8:6]=(Same As Above)
[B8:5]=SB PullUp Compensation   0=Auto 1=Manual
[B8:4]=SB PullDn Compensation   0=Auto 1=Manual
[B8:3]=SB PullUp Compensation
[B8:2]=(Same As Above)
[B8:1]=SB PullDn Compensation
[B8:0]=(Same As Above)

[B9:0]=VLink Slew Rate Control  0=Disabled 1=Enabled

[BE:7]=MECC Drive               10=Medium 11=Highest
[BE:6]=01=Lower                 00=Lowest

[BF:7]=MA/SCMD Pin Toggle Redux 0=Disable 1=Enable
[BF:6]=Slew Rate Ctrl MA/SCMD A 0=Disable 1=Enable
[BF:5]=Slew Rate Ctrl MA/SCMD B 0=Disable 1=Enable
[BF:3]=DIMM #3 MAA/MAB Select   0=MAA     1=MAB
[BF:2]=DIMM #2 MAA/MAB Select   0=MAA     1=MAB
[BF:1]=DIMM #1 MAA/MAB Select   0=MAA     1=MAB
[BF:0]=DIMM #0 MAA/MAB Select   0=MAA     1=MAB

[C0]=Power Management           Capability ID

[C1]=Power Management           New Pointer

[C2]=Power Management           Capabilities

[C3]=Power Management           Capabilities II

[C4:1]=Power State              10=Unknown 11=D3 Hot
[C4:0]=01=Unknown               00=D0

[C5]=Power Management Status

[C6]=PCI-to-PCI Bridge          Support Ext

[C7]=Power Management Data

[F0:0]=UnDoc'ed Mem enhancement?

[F1:5]=UnDoc'ed PCI enhancement?

[F5:7]=Back Door Revision ID
[F5:6]=(Same As Above)
[F5:5]=(Same As Above)
[F5:4]=(Same As Above)
[F5:3]=(Same As Above)
[F5:2]=(Same As Above)
[F5:1]=(Same As Above)
[F5:0]=(Same As Above)

[F6:7]=Revision ID
[F6:6]=(Same As Above)
[F6:5]=(Same As Above)
[F6:4]=(Same As Above)
[F6:3]=(Same As Above)
[F6:2]=(Same As Above)
[F6:1]=(Same As Above)
[F6:0]=(Same As Above)

[F7:7]=Foundry ID
[F7:6]=(Same As Above)
[F7:5]=(Same As Above)
[F7:4]=(Same As Above)
[F7:3]=(Same As Above)
[F7:2]=(Same As Above)
[F7:1]=(Same As Above)
[F7:0]=(Same As Above)

[FC:0]=Back Door                0=Disabled 1=Enabled

[FE:7]=Back Door Device ID 8-15
[FE:6]=(Same As Above)
[FE:5]=(Same As Above)
[FE:4]=(Same As Above)
[FE:3]=(Same As Above)
[FE:2]=(Same As Above)
[FE:1]=(Same As Above)
[FE:0]=(Same As Above)

[FF:7]=Back Door Device ID 0-7
[FF:6]=(Same As Above)
[FF:5]=(Same As Above)
[FF:4]=(Same As Above)
[FF:3]=(Same As Above)
[FF:2]=(Same As Above)
[FF:1]=(Same As Above)
[FF:0]=(Same As Above)

11063147.pcr

Code:

[COMMENT]=Made by NEOAethyr.
[MODEL]=VT8367 (KT333CE)
[VID]=1106:VIA
[DID]=3147:LPC Bridge

[00:7]=Vendor ID
[00:6]=(Same As Above)
[00:5]=(Same As Above)
[00:4]=(Same As Above)
[00:3]=(Same As Above)
[00:2]=(Same As Above)
[00:1]=(Same As Above)
[00:0]=(Same As Above)

[01:7]=Vendor ID
[01:6]=(Same As Above)
[01:5]=(Same As Above)
[01:4]=(Same As Above)
[01:3]=(Same As Above)
[01:2]=(Same As Above)
[01:1]=(Same As Above)
[01:0]=(Same As Above)

[02:7]=Device ID
[02:6]=(Same As Above)
[02:5]=(Same As Above)
[02:4]=(Same As Above)
[02:3]=(Same As Above)
[02:2]=(Same As Above)
[02:1]=(Same As Above)
[02:0]=(Same As Above)

[03:7]=Device ID
[03:6]=(Same As Above)
[03:5]=(Same As Above)
[03:4]=(Same As Above)
[03:3]=(Same As Above)
[03:2]=(Same As Above)
[03:1]=(Same As Above)
[03:0]=(Same As Above)

[04:7]=Address / Data Stepping  1=Wait Cycles Enabled
[04:6]=Parity Error Response    0=Disabled 1=Enabled
[04:5]=VGA Palette Snoop        0=Disabled 1=Enabled
[04:4]=Mem Write&Invalidate CMD 0=Disabled 1=Enabled
[04:3]=Special Cycle Recognition0=Disabled 1=Enabled
[04:2]=Bus Mastering            0=Disabled 1=Enabled
[04:1]=Memory Access            0=Disabled 1=Enabled
[04:0]=I/O Access               0=Disabled 1=Enabled

[05:1]=Fast BackToBack Cycle    0=Same Only 1=Diff Allow
[05:0]=System Error Line (SERR#)0=Disabled 1=Enabled

[06:7]=Fast BackToBack Capable  0=No Support 1=Supported
[06:6]=User Definable Features  0=No Support 1=Supported
[06:5]=66MHz Capable            0=No Support 1=Supported
[06:4]=New Capability List      0=No Support 1=Supported

[07:7]=Detected Parity Error    0=None 1=Error
[07:6]=Signaled SystemError Line0=None 1=Error
[07:5]=Received Master Abort    0=None 1=Aborted
[07:4]=Received Target Abort    0=None 1=Aborted
[07:3]=Signaled Target Abort    0=None 1=Aborted
[07:2]=Device Select Timing     10=Slow 11=Unknown
[07:1]=01=Medium                00=Fast
[07:0]=Data Parity Error        0=None 1=Error Detected

[08:7]=Revision ID
[08:6]=(Same As Above)
[08:5]=(Same As Above)
[08:4]=(Same As Above)
[08:3]=(Same As Above)
[08:2]=(Same As Above)
[08:1]=(Same As Above)
[08:0]=(Same As Above)

[09:7]=Programming Interface
[09:6]=(Same As Above)
[09:5]=(Same As Above)
[09:4]=(Same As Above)
[09:3]=(Same As Above)
[09:2]=(Same As Above)
[09:1]=(Same As Above)
[09:0]=(Same As Above)

[0A:7]=Sub Class
[0A:6]=(Same As Above)
[0A:5]=(Same As Above)
[0A:4]=(Same As Above)
[0A:3]=(Same As Above)
[0A:2]=(Same As Above)
[0A:1]=(Same As Above)
[0A:0]=(Same As Above)

[0B:7]=Base Class
[0B:6]=(Same As Above)
[0B:5]=(Same As Above)
[0B:4]=(Same As Above)
[0B:3]=(Same As Above)
[0B:2]=(Same As Above)
[0B:1]=(Same As Above)
[0B:0]=(Same As Above)

[0C:7]=Cache Line Size
[0C:6]=(Same As Above)
[0C:5]=(Same As Above)
[0C:4]=(Same As Above)
[0C:3]=(Same As Above)
[0C:2]=(Same As Above)
[0C:1]=(Same As Above)
[0C:0]=(Same As Above)

[0D:7]=Latency
[0D:6]=(Same As Above)
[0D:5]=(Same As Above)
[0D:4]=(Same As Above)
[0D:3]=(Same As Above)

[0E:7]=Header Type
[0E:6]=(Same As Above)
[0E:5]=(Same As Above)
[0E:4]=(Same As Above)
[0E:3]=(Same As Above)
[0E:2]=(Same As Above)
[0E:1]=(Same As Above)
[0E:0]=(Same As Above)

[0F:7]=Built In Self Test       0=No Support 1=Supported
[0F:6]=Initialize               Built In Self Test
[0F:3]=Completion Status
[0F:2]=(Same As Above)
[0F:1]=(Same As Above)
[0F:0]=(Same As Above)

[2C:7]=Sub Vendor ID
[2C:6]=(Same As Above)
[2C:5]=(Same As Above)
[2C:4]=(Same As Above)
[2C:3]=(Same As Above)
[2C:2]=(Same As Above)
[2C:1]=(Same As Above)
[2C:0]=(Same As Above)

[2D:7]=Sub Vendor ID
[2D:6]=(Same As Above)
[2D:5]=(Same As Above)
[2D:4]=(Same As Above)
[2D:3]=(Same As Above)
[2D:2]=(Same As Above)
[2D:1]=(Same As Above)
[2D:0]=(Same As Above)

[2E:7]=Sub Device ID
[2E:6]=(Same As Above)
[2E:5]=(Same As Above)
[2E:4]=(Same As Above)
[2E:3]=(Same As Above)
[2E:2]=(Same As Above)
[2E:1]=(Same As Above)
[2E:0]=(Same As Above)

[2F:7]=Sub Device ID
[2F:6]=(Same As Above)
[2F:5]=(Same As Above)
[2F:4]=(Same As Above)
[2F:3]=(Same As Above)
[2F:2]=(Same As Above)
[2F:1]=(Same As Above)
[2F:0]=(Same As Above)

[40:3]=DMA MultiPlier  1=1/1 ISA                0=1/2 ISA
[40:0]=ISA MultiPlier  1=1/2 PCI                0=1/4 PCI

Edit:
I will look up the optimal latency in a sec..
If you're using agp video, use 64 clocks for the latency to it, or 0x40 in hex.
Register 0x0d I believe, for vga card it's self I think, or maybe the agp or north bridge.
I'm starting to think it was vga.

**zoson** · 05-07-2014, 07:26 AM

vcore and memory voltage detection is off.
BIOS vcore is set to 1.3875v - CPU-Tweaker detects 1.416v - CPUz says 1.382v
BIOS memory is set to 1.575v - CPU-Tweaker detects 1.664v - HWMonitor shows 1.574v

It would seem CPU-Tweaker is detecting VIN0 as vcore.
No idea where it's getting the memory voltage.

**Fritz_the_germ** · 01-19-2023, 07:52 AM

Hope you will like this:

Thread: New Memory Tweaker for Intel Chipsets

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