New Memory Tweaker for Intel Chipsets

[boblemagnifique]

Great Work Hervé

[RPGWiZaRD]

Just wanna thank you once again for your work on this absolutely wonderful program which I've been using instead of BIOS for quite a while now and newer versions coming along nicely.

[Monstru]

Finnaly a tool for Nehalem? WOOOT...me goes tweaky, tweaky on my platform now

[mikeyakame]

Felix,

Intel X38/48 possibly P45.

MCHBAR 0x23E,0x63E [4:0]

Common Performance Level Read Phase Advance Channel A, Channel B (Phase Pull in)

0x0000000000000000b = 0T phase advance
0x0000000000000001b = 1T phase advance, pull in phase 1
0x0000000000000011b = 3T phase advance, pull in phase 1 + 2

and so on.

From the divider with most active phases I could think of, 12:10.

Read Delay Phase adjust = +31T or pull in on all 5 phases. 0x0000000000011111b ( 0x1fh)
Read Delay Phase adjust = 0T / Neutral , no pull in on any phases. 0x00h

For 12:10 divider, 5 Phases / Channel. Phase 1 lowest bit, Phase 5 highest bit. 2 Phases would only set [1:0], 3 Phases would set [2:0]

0x249 PL = 8
FED14240 01001100 00052310 0E840800 00392200
0x649 PL = 8
FED14640 01001100 00252310 0E840800 00392200

Pull in 1,2,4,5 cha +27T Read Phase Delay Adjust
FED14230 00000000 00000000 00001300 001B7A89
Pull in 1,4,5 chb +25T Read Phase Delay Adjust
FED14630 00000000 00000000 00001300 00197A89

No pull in cha Neutral Read Phase Delay Adjust
FED14230 00000000 00000000 00001300 00007A89
No pull in chb Neutral Read Phase Delay Adjust
FED14630 00000000 00000000 00001300 00007A89

All pull in cha +31T read phase delay adjust
FED14230 00000000 00000000 00001300 001F7A89
all pull in chb +31T read phase delay adjust
FED14630 00000000 00000000 00001300 001F7A89

Dont know if this interests you but was just going through some mchbar dumps to figure out what values Asus AI bios settings change, and figured out this value! Each channel a/b (0x230/0x630) pair from same MCHBAR dump

0x510h[7:0], 0x910h[7:0] appear to hold Dimm 1 & 3 (A1 and B1) clock fine delay
FED14510 00009635
0x510h[15:8], 0x910h[15:8] appear to hold Dimm 2 & 4 (A2 and B2) clock fine delay
FED14910 00009434

0x511h[15:0] 0x911h[15:0] both hold another 2 delay values for a1,a2 and b1,b2 , and the following rows also hold what are possibly strobe related offset / adjustments.

which register holds the command rate value for an x38/48 mch?

[FELIX]

Thank, all these registry values are interesting, but I don't know how I can add this settings in memset actually.
The only solution will be to change (and enlarge) the interface, but it's a hard job, and I have no time for now.Perhaps at next time...

a question: whats settings have the more impact on performance?

For command rate, it's not define:
On Asus motherboard, it's at FED140A0 bit 4

On Abit motherboard, it's at FED140C0 bit 17

[dinos22]

felix

cas# reports properly now thanks
Gigabyte X58-UD5

[dinos22]

just testing some more
its misreporting TRAS

set in bios 24
showing 26

also is it possible to change these subtimings. The app is not allowing me to set new changes............all the buttons are grayed out

[FELIX]

...strange, cause tRAS is correctly reported on others motherboard.Perhaps a bios bug.
Is cpu-z report correctly the tRAS?

For timings change, coming soon with the finale release.

[dinos22]

i will do some more testing and will report

[saaya]

aweseome tool herve!!!

[FELIX]

...I have a full version ready for read and write, but never tested on NHM.
If someone is interesting to test it, send me a email address by PM.

[Woody-san]

@FELIX

YGPM.

Thanks,
;-)

[Monstru]

You've got PM

[dinos22]

just modded my board and sprayed plastic spray
will bench tomorrow and test this final version and report

[rge]

had to change dpi to 96 to test...but works fine on mine for main timings. changed values around. Each pic shows exactly what was set in bios for CL, tRCD, tRP, tRAS.

Other timings, tRRD set manually to 4 in bios (just make sure was at 4) says 6 in cpuz tweaker, constantly reads +2 too high. I set tRFC manually to 48 in bios cpu tweaker says 50, if set to 50 in bios it says 52. Round trip latency also reports +2 higher than what I set manually.

Of note if testing, have to set values manually b/c if at auto, just b/c auto normal value is listed to left, does not mean that is value you are at with auto. For example, tRFC on auto (value to left on x58 GB bios says 48) but cpu tweaker reads 62. Then I set manually on 48 and cpu tweaker reads 50. If set manually on 60, cpu tweaker says 62.

[FELIX]

...have you tried to change one timing (tRAS for example) under win and checked that the change take effect with cpuz?
I fear that it is not working (registers locked in write)

[rge]

...have you tried to change one timing (tRAS for example) under win and checked that the change take effect with cpuz?
I fear that it is not working (registers locked in write)

Nope, I just tested if it reads correctly from what is set in bios.

I just tried making changes in windows with it, it does not work. Changing tRAS, tRCD, or tRP with cpu-tweaker does not change the value in cpuz.

[FELIX]

...OK, PCI registers are locked.
I just completely terminated the software, and I learn that it don't work: too bad.
I'll speak about it with Franck, and eventually send an email at Intel, but not a lot of chance to succeed...

The link (if others users want to test it):
http://www.tweakers.fr/download/CPU-Tweaker.zip
But probably don't work.

[dinos22]

oh
looks like we are stuck with long arse bios RAM tweaking

yeah i also got +2 on Tras when i set it to 24 in bios

[mikeyakame]

Felix,

Are the I7 timings held in the CPU MSR's?

[FELIX]

-> rge: trrd,trfc and round trip latency reading fixed in this version: CPU-Tweaker.zip

-> dinos22: probably a bios bug: tRAS is correctly reading on others motherboards.

-> mikeyakame: no, timings held in the PCI configuration space, like K10.

[dinos22]

seems tras is a weird bug

and confirmed
cant change timings with latest version

[mikeyakame]

Felix,

One thing we know is, OE Software like Asus TurboV and Gigabytes OC software both allow memory timings to be changed on the fly, so it's just a matter of figuring out the means they use through software and take a similar path right?

Hmm, possibly the difference in tRAS between bios and PCI register value may be due to an arbitrary minimum turnaround before an ACT command can be issued, and bios has been coded to account for this but not actually display it because it's a preamble thats default. Just throwing ideas around.

[FELIX]

...right, perhaps registers are simply locked by a bit somewhere in the PCI space.
But you sure that these soft allow to change timings in the fly on Core i7?

[DMF]

The frequency difference doesn't bother me (much) either. But the report of DDR3 most definitely does.

Could you try with the last beta...

Yes, that fixed it. But the FSB is still reported a little low (e.g. 421 v. 432).


Thanks!