It's useful for my 845PE?
It's useful for my 845PE?
Perhaps not.Originally Posted by FELIX
Write recovery time is actually what you call "Write to Precharge Delay" but you are showing wrong value for it.Originally Posted by FELIX
Haven't tried them, Read delay is usefull for example.Originally Posted by FELIX
I know where that extra .1s in SPi 1M is coming from now Thanks for the very cool app Felix!
On a side note, you might want to include version numbers if you are going to be doing substantial updates so we can keep track of what's new or old
"Write recovery time is actually what you call "Write to Precharge Delay"
but you are showing wrong value for it."
I'm not show wrong value,I show the value for a Write to Precharge command delay,
And this value = Cas - 1 +BL/2 + tWR.
BL=Burst length (Always 8)
tWR is Write Recovery time.
See On your Link:"The Write Recovery Time memory timing determines the delay between
a write command and a precharge command is set to the same bank of memory."
I include that in the next version.Originally Posted by boostedevo
Thanks for making Memtest
By any chance would you be able to add support for PAT (Performance Mode) over 200Mhz FSP on the P4P800-SE (i865PE) and/or with Memory Dividers being used?
Last but not least would you be able to add the selection for Dual Chanel Dynamic mode?
Details here http://www.intel.com/design/chipsets...s/25252304.pdf
Sorry,it's not possible to add these options in a software.
can you add support for i855pm chipset??
Originally Posted by metro.cl
Perhaps in a next version.
Possible to add support for 845 and 855 chipsets,
but I need time to do that.
Felix I thought the trick to applying PAT over 200Mhz FSB was applying the 533Mhz bootstrap?Sorry,it's not possible to add these options in a software.
It is a shame these options are not available by software
Could you add the DRAM Idle Timer. (Common Options : 0T, 8T, 16T, 64T, Infinite and Auto) to your utility?
Any chance of more tweaks and features being implemented for the i865PE/875P chipset in future versions?
By the way folks Felix updated Memset on the 21-3-2006 (see the first post).
Ok great... we needed this.. but as you said that channel a + b have to be the same... cant you edit so when setting something it will occur on both channels?
that is a little bit easyer
*EDITed by IFMU*
Signature Removed by XS Staff for not following XS Policies
Beta67-> for Pat some bits are Read/Write,but some bits are Read Only,
and I can't change them.
For Dram Idle Timer,I add it in a next version.
Last edited by FELIX; 03-27-2006 at 10:55 AM.
Thx for this GREAT tweaker felix, i really like it
I did some testing with 2x512mb crucial ballistix pc3200 (micron 5B G) and a p4p800se (i865), I tested the effects of CpC and Read delay. The txt is in the attachment
Great program Felix. Has anyone increased their scores with it.? Maybe post some before and after results?
Hey proth, you can definitely see results in Sandra bandwidth tests, but it will definitely take some testing and tweaking for various things. In some cases, "looser" provides gains for me (>DDR1000 / 4-3-2-4).
The increases in bandwidth aren't overtly noticeable in say SPi 1M, but you can definitely see something in the longer ones like 4M or 8M. I haven't tried a 32M with it yet...should be some decent gains though.
Have you tried changing any of the settings apart from the traditional tCL, tRTC, tRP, and tRAS..Seems like the only benefit is "on the fly" tweeking instead of BIOS changes and reboots. Don't get me wrong...On the fly tweeking is FANTASTIC....Originally Posted by boostedevo
Yes, I play with mostly all except those. Actually, maybe twice I messed with them, but can't do any better than I boot with, so I leave them alone and concentrate on the others.
A few years ago I designed and coded a small Motorola Coldfire 5272 CPU, Micron SDRAM and Intel StrataFlash. The CPU had a built in SDRAM controller and I used the default init code from MICRON which was good enough for what had to be done. I took a look at the app note for SDRAM, which had similar timing and setup parameters to DDR2, and remember the timing and configuration was really bizzare although it was a piece of cake to interface to on the hardware side. Think I'll dig up that app note again and try to make some more sense out of it and and what parameters are critical to performance. YUCK.. Precharge delay, page close timers, null clocks between READ/WRITE commands, all crap I never cared to fully understand
Great program! Best memory tweaker for i875/i865 chipsets there has ever been. Thanks mate.
Used it on my Asus P4C800-E Deluxe i875 chipset and dropped my 2GB of BH-5 latency by a lot at just 217MHz. Appears to be totally stable.
Went from 72ns to 62ns latency by changing just the:
- Read Delay (tRD) from 5 down to 4
- Read Delay adjust from disable to enable
Maybe this is what Abit did with the AI7 boards to create GAT settings such as street racer and F1.
Later on changed a few other of the *write settings near the bottom, and I suspect it has yeilded improved write bandwidth (cannot comfirm this right now)
Last edited by deltarealm; 03-27-2006 at 07:40 PM.
Intel Core 2 Quad Q9550 ' G.Skill 8GB DDR2-1000 ' Gigabyte GA-X48-DS5 ' Nvidia GTX 275
I take it Beta67 is the one available in your first post?
HiOriginally Posted by FELIX
I guess the idea of tweaking PAT is out of the window, never mind. It's a shame there is no way to edit/mod the BIOS *.rom file to eneable PAT over 200Mhz FSB before flashing. Thanks for looking into the DRAM Idle timer options. Im looking forward to see what is in store for us with the version.
Keep up the good work Felix
The first post of this thread was edited on the 21-3-2006 on that day Felix updated the version of his Memset. Download it and see the difference, the newer version has even more things to play with
wow GREAT little program! Much more extensive than the old i865/875 tweaker.
Very nice, good job!
Dothan Power :p
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