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Thread: New Memory Tweaker for Intel Chipsets

  1. #351
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    EVGA 680i: Twtr is reading 1 number low.

    When Twtr is set to 8T; Memset3.1 reads 7T. Everything else is OK.

    Beta did that also...
    Last edited by JWilson; 01-02-2007 at 09:14 AM.
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  2. #352
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    ->jWilson:I fix that soon.
    ->webwilli,joe_cool:I send you an MP.

  3. #353
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    Biostar 965PT and Gigabyte 965P-S3:

    Twr, Twtr, Trrd, and Trtp BIOS settings do not agree with Memset readings, but I believe the BIOS on both boards are wrong. The 2 boards when set to the same memory timings, display different Memset readings and different from each other. Memset readings agree with MCHBAR register readings.

    I haven't looked at DFI 975X yet.
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  4. #354
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    will give it a go
    Lol Dead

  5. #355
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    Thanks for the program Felix.

    I accidentally hit "save" instead of "apply" and had a stressful time trying to get my XP to boot properly again. Finally fixed by saving new settings while XP was still loading up (I guess before the old settings were loaded as XP would crash after a few of the tray icons were loaded).

    I see that there is no program to remove in XP's control panel "add and remove" and there is no uninstall feature. Is simply deleting the program from the folder enough or is the saved settings still existing somewhere?

    Thank you in advance.
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  6. #356
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    Possible,check in C:/ if a folder MemSave exist, and eventually delete the file,
    and delete the icon in the startup folder.

  7. #357
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    Any support for 650i ?

    Regards

    Martin


    Life sometimes gets in the way of what we want to do.

  8. #358
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    ...possible,I send you an MP.

  9. #359
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    Quote Originally Posted by FELIX
    Possible,check in C:/ if a folder MemSave exist, and eventually delete the file,
    and delete the icon in the startup folder.
    Thanks Felix. Keep up the good work!
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  10. #360
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    Already Felix received register dump and add support for low price chipset nV 650i.

    Big thank's



    Regards
    Martin
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  11. #361
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    Sorry if this was already answered, but I didn't read the entire thread.

    Is it possible to disable mchbar locking when using the save function?

  12. #362
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    No,it's not possible.
    I try to add it in a next version.

  13. #363
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    Question for you Felix:

    Why on Intel 975 it is not possible to set the following:

    tRC - Min. Active to Active Auto Refresh Tme
    tRRD - Min. Row Active to Row Active Delay
    tWR - Write Recovery Time
    tWTR - Internal Write to Read Command Delay
    tRTP - Internal Read to Precharge Command Delay

    Those are the settings which BIOS can read from SPD and set although I am not sure if those timings are set in MCH or by sending the commands directly to the RAM modules itself. Latest version of Everest (3.50.865) beta shows their values from SPD in case you want to check them out. It would be nice to be able to set them manually.

    There is also a program Thaiphoon Burner which lets you examine all SPD timings and even reprogram SPD EEPROM.

    Word of caution to everyone: Some SPD timings are linked to the frequency (cycle time) and it is not possible for example to set tRAS independently in those tables. If you change tRAS for highest frequency in the table, then your lower frequencies may get tRAS value which is too low. If it ever happens that you need those low frequencies, for example when you reset CMOS or your mainboard goes into recovery mode your system may refuse to boot. Do not tinker with SPD if you don't know exactly what you are doing!!!

  14. #364
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    audiofreak: simply because tRC,tRRD,tWR,tWTR & tRTP are not present
    in 9XX chipsets.
    Intel prefer to integrate external timings (commands delay) in these chipsets
    whereas AMD or NVidia prefer to integrate internal timings.

  15. #365
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    hi FELIX,

    there is still the problem with locking/unlocking of mchbar in version 3.1.

    if i exit memset by clicking the [Exit] button in the lower right corner, some other programs like cpu-z, everest reports wrong figures for memorytimings!

    if i exit memset by licking the [X] button at the upper right corner, everything is fine!

    have a look at your code whats the difference in exiting your program this two ways!

    the problem is, that if i use the [Save] button to apply the settings automatically at startup, your program is using the first method to exit after setting the timings at startup. this results in the problem described above!

    anyway, a great tool to adjust timings! thanks FELIX
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  16. #366
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    With 975x chipset??

  17. #367
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    Quote Originally Posted by FELIX
    With 975x chipset??
    sorry for not stating it clearly enough: yes 975X chipset!

    well, it's not that big deal as long as you are using memset manually, cause as long as you know whats going on, its easy to hit the right button to exit memset properly.

    the annoying part is the way memset exits when it is run during startup. there is no way to influence how memset exits. so there is no way to get around this issue without starting memset manually afterwards as described in my previous post.

    FELIX, you obviously are exiting your program trough two different doors ...

    ps. wasn't sure if you are still monitoring this thread - quick reply!
    thanks again FELIX, you did a great job on this program anyway!
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  18. #368
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    I know that the same problem exist with 965 chipset (Read post #234 on this thread.) but it's the first time I see that on 975 chipset...
    I try to fix that in a next version.
    Last edited by FELIX; 01-26-2007 at 03:24 AM.

  19. #369
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    Quote Originally Posted by FELIX
    I know that the same problem exist with 965 chipset (Read post #234 on this thread.) but it's the first time time I see that on 975 chipset...
    I try to fix that in a next version.
    have read post #234 as the whole thread!

    unfortunately this problem exists also on 975X chipsets!

    as i said FELIX, i don't care too much about the behavior of the [Exit] and [X] buttons. what would help, is the behavior of the program when it exits during usage at startup ...

    THANKS
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  20. #370
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    i can't get 64-bit version.

  21. #371
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    Quote Originally Posted by FELIX
    audiofreak: simply because tRC,tRRD,tWR,tWTR & tRTP are not present
    in 9XX chipsets.
    Intel prefer to integrate external timings (commands delay) in these chipsets
    whereas AMD or NVidia prefer to integrate internal timings.
    I am not sure I understand what you mean by this.

    How those timings get programmed on Intel then? The RAM wouldn't work without them, right?

  22. #372
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    Here is the 3.2 version:
    MemSet32

    -Work on 2000 /XP 32&64 /Vista 32.
    -Add "olds" chipsets:
    Intel 815
    NForce2
    Via KT266/333/400
    -Disabled change Cas# on DDR2.(didn't work, and crash)
    -Some bug fixed.

    Tell me if you find bug with this version...
    Last edited by FELIX; 02-20-2007 at 01:43 PM.

  23. #373
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    Many thanks FELIX
    lots and lots of cores and lots and lots of tuners,HTPC's boards,cases,HDD's,vga's,DDR1&2&3 etc etc all powered by Corsair PSU's

  24. #374
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    Asus P5N-E SLI nvidia 650i

    "The Driver TVicPort Can Not Be Found"

    that happens everytime i try to run the program.

    tvicport.dll & .sys are right there in the folder with the exe.
    "These are the rules. Everybody fights, nobody quits. If you don't do your job I'll kill you myself.
    Welcome to the Roughnecks"

    "Anytime you think I'm being too rough, anytime you think I'm being too tough, anytime you miss-your-mommy, QUIT!
    You sign your 1248, you get your gear, and you take a stroll down washout lane. Do you get me?"

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  25. #375
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    "The Driver TVicPort Can Not Be Found"

    Exactly the same thing with me.

    ABIT AW9-D MAX.

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