How to use the Zippy and 850SSI on DFI nF4 - 56K caution

[EMC2]

j/k, the explanation of the bypass cap and surge current explanation is from emc2, not from me, and i didnt give him a hint about jp17

but steven IS a smelly rice-eater!
prepares for

Why Saaya, you, YOU, YOU swine! Just for that, I'm gonna show them the photo Steven took of you this morning

[RAMMIE]

@EMC2,

Yes, way You see... We have plenty of great OCers, skilled tweakers, xtreme phase-change builders, some BIOS modders but very few true hardware experts and volt-modders, with enough technical knowledge of PC design and electronics to figure stuff on their own.
With that said, I stand behind what I said

I agree. This is great detective work.Now I can use my Zippy to it's full potential.

[evil_raver]

EMC2 thanx so much for sharing that great info with us....

[saaya]

it wasnt the rice daniel, and it wasnt the bockwurst (b o c k, no r ) that made me go down like a fat swine it was the sake steven gave me! my head stil hurts!
but it tasted so damn sweet...

[Dave in Daytona]

A very good presentation.

Excellent work!

Thanks,
Dave

[Ender17]

great work
and nice PSU, BTW

[Dumo]

Where I put my Zippy? ...EMC2 thanks for the info...

[jikdoc]

my similar trick to get the zippy to work on 5v mode with dfi was just plain blind trial and error. if i remember correctly, i ended up covering all the pins and it booted up with the 5v dimm options. i was able to pass memtest at 3.4v with utt, but whenever i tried to enter windows i'd get bsod. after this experience i tried some variations on that and eventually was able to boot into windows but with serious stability problems. what i do remember is that i didn't use the configuration that daniel figured out. i remember trying to play with the 5vsb jumpers, either turning them off or on. i gave up trying to figure it out since the rig i was playing with is both my everyday rig and my overclocked rig and i couldn't afford more downtime.

i'll try out my utt tomorrow with daniel's settings. i'm glad i stuck it out with the zippy and this dfi board. now i don't have to wait for hipro's maximizer or dfi's version of the ati board to play with utt.

[Malves]

Hey Dani,

Nice job, bro.

[MaxxxRacer]

does this mod help with vdimm stability or is it entirely a fix for the zippy psu problem?

[EMC2]

does this mod help with vdimm stability or is it entirely a fix for the zippy psu problem?

This is pretty much only for allowing people with PCPnC 850SSI and Zippy 700W PS's to use the 5V rail for generating memory voltages without having to resort to tweaking their 3.3V rail... though it might help in other ways.

Regarding Vmem stability... as long as you have a good PS, keep the control FETs cooled properly, and stay less than 200mV below the input power rail used for Vmem generation you will have stable Vmem power during continuous operation. I've logged it with a Fluke and see less than 20mV DC deviation from no load to full load and all points in between with memory speed maxed and latency minimized.

However... if you let those FETs get too hot, it can start showing instability... and if you push closer than 200mV of the input supply rail it can as well. Here's a chart showing why you want to maintain that 200mV margin from the input supply rail on Vmem:

Charted voltages on DFI nF4 with a 3.3V rail that measured 3.31V actual


When you get to the point on the right side of the chart, the control voltage on the FETs is wide open... any spikes on the input rail will pass right through... as well as there being fluctuations in Vmem due to load changes. The same situation applies when using a tweaked 3.3V rail at higher voltages or when using the 5V rail (only with the 5V rail you're ok up to about 3.8V).

*EDIT* Here are pics showing the real thing

[wtz54321]

When you get to the point on the right side of the chart, the control voltage on the FETs is wide open... any spikes on the input rail will pass right through... as well as there being fluctuations in Vmem due to load changes. The same situation applies when using a tweaked 3.3V rail at higher voltages or when using the 5V rail (only with the 5V rail you're ok up to about 3.8V).

So you did measured there are voltage fluctuations when we use 3.3V rail and 3.2V setting in bios ?

I have a problem ...

How to ensure that the 1st and 2nd control voltage will remain the same as your chart when the input voltage rail got fluctuations , and makes it pass through the transistor ?

[EMC2]

wtz54321 - Yes.

Sorry bro... not quite sure what you're asking with 2nd Q Are you asking how to intentionally get the circuit in drop-out so you can feed fluctuating source voltage thru it? If so, why? If not... could you try to rephrase please

Peace

[wtz54321]

wtz54321 - Yes.

Sorry bro... not quite sure what you're asking with 2nd Q Are you asking how to intentionally get the circuit in drop-out so you can feed fluctuating source voltage thru it? If so, why? If not... could you try to rephrase please

Peace

As far as I know , most of the linear regulator is designed with a OP AMP
to adjust the gate voltage of the MOSFET ... And the control voltage will
change according to the feedback point from the output voltage ... If the
output voltage changed , the control voltage will be changed ...

So if there is voltage spike generated to cause the output voltage higher
than the set point , the OP AMP will change the control voltage of the
MOSFET to prevent the output voltage followed by the input voltage ...

If possible , try to adjust the 3.3V rail dynamically , and see if the control
voltage changed ... If the answer is yes , whether the spike will pass through
the MOSFET or not will depend on how fast the OP AMP is ...

[mcnbns]

EMC2, thank you so very much for this fix! While I don't have a Zippy or PCP&C 850W unit, it seems to help a lot with my OCZ Powerstream 520W.

The power turned off for a few minutes half an hour ago and I couldn't boot my comp after the power came back on. Clearing CMOS didn't work... then I remembered the "cold boot" issue with VDIMM starting really low.

When the power came back on I checked this thread on my bro's comp and did the jumper thing. Booted on the first try!

[wtz54321]

Some linear regulator circuit I found ...
http://japan.maxim-ic.com/appnotes.c...ote_number/139
The control voltage of MOSFET is driven by the OP AMP , and the OP AMP
will change the control voltage dynamically ... If the input voltage changed
and the output voltage followed by it , once the OP AMP sense the change
of the output voltage , it will change the control voltage immediately to
prevent the OP AMP two input pin has two different voltage ... So how fast
OP AMP the regulator use will determine the output voltage variation ...

[EMC2]

--- wtz --- When you're in the normal band of the regulator, yes it will...

There's two issues here tho... one deals with the bandwidth of the circuit used... the other deals with the point the control voltage is at and the slew rate of the output

BTW... you're suggestion to tweak the 3.3V rail and see if it tracks is far from a proper way to test the transient response of the regulator - even when it isn't in drop-out.

--- mcnbns ---

The jumper configuration I gave does nothing for the "cold boot" issue... Vmem will still be at a low (2.4V to 2.6V) level after a AC on/off cycle. What you saw was sheer coincidence bro, but thanks anyway That being said... based on certain events tonight and some things I'm looking at now, for totally different reasons I may be suggesting that jumper config for anyone depending on further tests...
Peace

[wtz54321]

--- wtz --- When you're in the normal band of the regulator, yes it will...

There's two issues here tho... one deals with the bandwidth of the circuit used... the other deals with the point the control voltage is at and the slew rate of the output

BTW... you're suggestion to tweak the 3.3V rail and see if it tracks is far from a proper way to test the transient response of the regulator - even when it isn't in drop-out.

That's for trying if the control voltage will vary from the output/input voltage change ...

If the control voltage will change , that means the OP AMP will try to
maintain the output voltage within a certain range ... Even there is a spike
generated in the input rail , it can still be controlled within a certain range ...
The whole spike will not pass completely from the input rail ... And the range
of the output voltage variation result will depend on how fast their OP AMP is
and the output slew rate ---> exactly what you refer to ...

[EMC2]

That's for trying if the control voltage will vary from the output/input voltage change ...

If it doesn't respond to slow changes, wouldn't be a regulator now would it

Regarding the rest... transient response in drop-out... analyze the circuit on the DFI nF4...

Oh... and for clarity regarding my "yes" to your first Q... please re-read what I said:

as well as there being fluctuations in Vmem due to load changes.

and note that the conditions under which it occurs...

Peace

[wtz54321]

If it doesn't respond to slow changes, wouldn't be a regulator now would it

Regarding the rest... transient response in drop-out... analyze the circuit on the DFI nF4...

Oh... and for clarity regarding my "yes" to your first Q... please re-read what I said:

and note that the conditions under which it occurs...

Peace

If the load changes and the regulator can not compensate it , that's the job for capacitor which is not possible done by any kinds of power circuit ... Linear regulator response time should be much faster than PWM ones ... Can you show us some picture you measured about the variation range you measured on this board ? We can take a look at if it's worse than we can imaginate ~~

Is it a undervoltage fluctuations or overvoltage fluctuations ? Or it's both ?

[mcnbns]

--- mcnbns ---

The jumper configuration I gave does nothing for the "cold boot" issue... Vmem will still be at a low (2.4V to 2.6V) level after a AC on/off cycle. What you saw was sheer coincidence bro, but thanks anyway That being said... based on certain events tonight and some things I'm looking at now, for totally different reasons I may be suggesting that jumper config for anyone depending on further tests...
Peace

Whoops.

I guess I must not have read your first post carefully enough. For some reason I thought this had to do with the cold boot issue. Oh, well. My comp is working again.

[uwackme]

I set this jumper config, and it cleared up the cold boot issue on my OLD BH5 and my Twinmos 3200 SP (UTT-CH) sticks.

THough I look forward to Oskar putting in a permanent fix in the bios.

[EMC2]

If the load changes and the regulator can not compensate it , that's the job for capacitor which is not possible done by any kinds of power circuit ... Linear regulator response time should be much faster than PWM ones ... Can you show us some picture you measured about the variation range you measured on this board ? We can take a look at if it's worse than we can imaginate ~~

Is it a undervoltage fluctuations or overvoltage fluctuations ? Or it's both ?

A capacitor can't do anything for a regulator in drop-out when the load demand increases and isn't of quite short duration Reset your thinking for a minute...

Regulator is at far right point on the original graph and is in drop-out. This means that the FET gates are being driven with the maximum voltage the control op-amp can generate and the FETs are hard-on... and they can not be driven any harder (like in the old Star Trek shows when Scotty says, "I'm giving ya all she's gawt Cap'ain" )

Now, the load current requirements change... remember, there is no more juice in the engines... and as a result the voltage drops - how much it drops is dependent on the magnitude of the increase in load current and the sum total of the effective resistance of the regulator series pass elements and parasitics. If the current demand is of a very short duration, the caps will help, but when the demand lasts past a point, the caps can't do diddly.

Here's three pics illustrating the point...

During boot, at the boot screen during scan for HDs:


During a low memory duty cycle - only background programs running:


During the running of Memtest T5, high memory duty cycle:


Now that is only with two 512MB DIMMs... it would be worse with two 1GB DIMMs or four DIMMs. Not a dangerous condition - but one that affects system stability and limits max MemClock frequency, especially in this case when you take into account the very narrow "sweet spot" of TCCx memory regarding Vmem (about 1/3 of the shown variation).

Regarding transient response, since I'm limited on time tonight, I'll leave you with this to ponder regarding the ability of the control op-amps to respond to relatively wide (not 10s of ns) duration transients of a positive nature... look at the level the control voltage is at and think about what it would/should be if the source voltage were high enough to not be in drop-out (and how far it must slew to get there)... then look at the slew-rate specs for the LM358 used, as well as their GBW and output drive current levels... then look at the gate charge specs for the control FET. Second point to ponder, negative transients on the supply rail... and remember, "She's giving it all she's got cap'ain"...

Oh....regarding linear vs PWM... depends on the circuits... newer high frequency advanced PWMs vs linear's with low slew rates and BW not necessarily true... however definitely less noise with equivalent filtering for the linear.

I set this jumper config, and it cleared up the cold boot issue on my OLD BH5 and my Twinmos 3200 SP (UTT-CH) sticks.

If it did, then your PS maybe coming into play (quite possible). Some Qs for you

1) Was your cold-boot problem the defined "occurs on initial boot after an AC on/off/on cycle", "stops at 3 LEDs lit", and "beeps continuously"?
2) If so, do you have a DMM?
3) If you do, would you please do the following:

a) Put your system in the same conditions where you had the cold-boot problem (AC off/on), instrument Vmem with the DMM, boot the system and see what Vmem is during POST.
b) Change the jumper back to the original position and repeat step (a)
c) Share your results please.

If it really helps, you'll find the voltage during (b) slightly lower than (a).

--- MCNBS --- Same would apply in your case

Oh... and what PS are you using?

Peace

[wtz54321]

All the above you refer to is the voltage drop situation due to the transistor is already in full on mode , and that's what I used to know , nothing special ...

But my question is the word you refer to ... " Spike " will pass through the transistor and the MOSFET control circuit will do nothing to this spile ...

Is that what you see with your board ?

[EMC2]

All the above you refer to is the voltage drop situation due to the transistor is already in full on mode , and that's what I used to know , nothing special ...

Then why the heck did you write post #45 And no, nothing "special"... just a cause for instable Vmem that limits max MemClock...

But my question is the word you refer to ... " Spike " will pass through the transistor and the MOSFET control circuit will do nothing to this spile ... Is that what you see with your board ?

The response time of the control circuit is 10usec for the second stage under the drop-out condition... ~1.5usec for the first stage. You end up with a several usec wide spike when it's a wide transient ( >=5usec wide) due to the response time of the control circuit.

Peace