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Thread: How tight can I run my TCCD with 300FSB?

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  1. #1
    Xtreme Member
    Join Date
    Mar 2005
    Montreal, Canada

    How tight can I run my TCCD with 300FSB?

    I'm running 300 x 9 2.5-3-3-7 @ 2.9v 1:1 1T, is it possible to do better (tighter)?

    So far, I failed. Any advises.


    FSB Bus Frequency: 300
    LTD/FSB Frequency Ratio: X 3.0
    LDT Bus Transfer Width: 16/16
    CPU/FSB Frequency Ratio: X 9.0
    PCI Express Frequency: 100 Mhz
    K8 Cool & Quiet Support: Disable
    CPU Vid Startup Value: Startup
    CPU Vid Control: 1.450v
    CPU Special Vid Control: Above Vid * 110%
    LTD Voltage Control: 1.20v
    Chipset Voltage Control: 1.50v
    Dram Voltage Control: 2.90v
    Run Memtest86: Disable
    MAC Lan: Auto
    MAC Media Interface: PinStrap
    Machine MAC NV Address: Disable
    Internal Phy SATA 1/2: Disable
    Internal Phy SATA 2/4: Enable
    Si I3114 sATA Raid Control: Disable
    VIA 1394 Control: Enable
    Marvel Giga Lan Control: Enable

    Dram Frequency: 200 (DRAM/FSB:1/01)
    Command Per Clock (cpc): Enable
    Cas Latency Control (tcl): 2.5
    Ras to Cas Delay (trcd): 3
    Min Ras Active Time (tras): 7
    Row Precharge Time (trp): 3
    Row Cycle Time (trc): 7
    Row Refrsh Cycle Time (trfc): 14
    Row to Row Delay (trrd): 2
    Write Recovery Time (twr): 2
    Write to Read Delay (twtr): 2
    Read to Write Delay (trwt): 2
    Refresh Period (tref): 3632
    Write Cas Latency (twcl): 1
    Dram Bank Interleave: Enable
    DQS Skew Control: Increase Skew
    DQS Skew Value: 255
    Dram Drive Strength Level: Level 7
    Dram Data Drive Strength: Level 2
    Max Async Latency: 0.8 nano seconds
    Read Preamble Time: 0.5 nano seconds
    Idle Cycle Limit: 256 Cycles
    Dynamic Counter: Disable
    R/W Queue Bypass: 16X
    Bypass Max: 7X
    32 byte Granularity: Disable (8 Bursts)

    Memtest86 36 passes (8hrs 25min) 0 errors.
    SuperPi 1M & 2M stable.
    Not Prime95 stable yet working on it.
    Last edited by Kosmic71; 05-06-2005 at 12:08 PM.
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