Thank you sxs112.
http://www.c627627.com/AMD/Athlon64/
(Refresh)
Thank you sxs112.
http://www.c627627.com/AMD/Athlon64/
(Refresh)
Last edited by c627627; 04-14-2005 at 11:49 PM.
Don't think he can OC because of the mobo..Originally Posted by shuRe
my badOriginally Posted by furyfax
sxs112, why don't you give GCPUID a shot, see how it works with your new chip?
Download GCPUID here
Member of Overclockers.com Folding @ Home team
"<The_Coolest> you can't unwaste wasted CPU cycles" - Start FOLDing now!
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AMD Ryzen 7 2700X / Mobo: Asrock Fatal1ty X470 / EVO 970 500GB + WD Blue 250GB + HDD / GPU: Dell RX 570 4GB / Mem: 2x16GB DDR4-3200 G.Skill 32GTZKW TridentZ - 32GB total / PSU: Seasonic Prime Ultra Gold 650W
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Core i7 2600K 3.4GHz @ 4.3GHz (Scythe Mugen2) / Mobo: Biostar TP67XE / 2x Inland Pro 120GB / GPU: HD5450 / Mem: 4x4GB DDR3-1600 G.Skill 8GBXL RipJawsX - 16GB total / PSU: Seasonic S12II 620W.
Core i3 540 3.06GHz @ 4.0GHz (Freezer 7 Pro) / Mobo: MSI H55M-ED55 / GPU: Integrated / Mem: 4x2GB DDR3-1600 G.Skill 4GBRL RipJaws - 8GB total / PSU: Antec 380W.
Core Temp - Accurate temperature monitor for Intel's Core/Core 2 and AMD64 processors
the cache is shared between the cores, physically its one block of cache from what i have seen, and the cores use HT links to access it
No its not, they are two seperate cores.
How hard is it to believe? they are two seperate K8 Venice/San Diego cores connected at the memory controller.
Last edited by The Coolest; 04-15-2005 at 03:46 AM.
Member of Overclockers.com Folding @ Home team
"<The_Coolest> you can't unwaste wasted CPU cycles" - Start FOLDing now!
Main rig:
AMD Ryzen 7 2700X / Mobo: Asrock Fatal1ty X470 / EVO 970 500GB + WD Blue 250GB + HDD / GPU: Dell RX 570 4GB / Mem: 2x16GB DDR4-3200 G.Skill 32GTZKW TridentZ - 32GB total / PSU: Seasonic Prime Ultra Gold 650W
Secondary rigs:
Core i7 2600K 3.4GHz @ 4.3GHz (Scythe Mugen2) / Mobo: Biostar TP67XE / 2x Inland Pro 120GB / GPU: HD5450 / Mem: 4x4GB DDR3-1600 G.Skill 8GBXL RipJawsX - 16GB total / PSU: Seasonic S12II 620W.
Core i3 540 3.06GHz @ 4.0GHz (Freezer 7 Pro) / Mobo: MSI H55M-ED55 / GPU: Integrated / Mem: 4x2GB DDR3-1600 G.Skill 4GBRL RipJaws - 8GB total / PSU: Antec 380W.
Core Temp - Accurate temperature monitor for Intel's Core/Core 2 and AMD64 processors
sorry. but there is no way that's right. why would they take up die space making an slow HT link between the cache and core now when they never did before?Originally Posted by reject
it's two seperate caches. i think all the cores will be made with 1mb+1mb, but any of them with a defect in the cache (likely, due to size) get cut down to 512kb+512kb
Got a fan over those memory sticks? No? Well get to it before you kill them
hmm so according to the newer roadmap only the 4800+ has 2mb of L2 and both the 4600+ and the 4800+ are 2.4 ghz.
Look at the picture in the post above yours. You're right, these are 2 seperate processing cores, with their own dedicated L1 and L2 caches, and the only place they meet is the memory controller.Originally Posted by ozzimark
I have to disagree with you on your statement that all cores will be 1mb+1mb, when clearly, already its not the case.
20F30 is a CPUID reading of a dual core 1MB+1MB CPU, the new DC Opteron have a 20F10 CPUID reading. The chip we see in this thread is 20FB1, which is not similar to either of these CPUIDs.
The 20F30 and 20F10 are like 2 San Diegos stuck together, this 20FB1 is like 2 Venices stuck together, there is no disabled L2 cache on this chip. I don't think I've ever seen an ES (and this is a semi-ES as it doesn't have a model number programmed into it, that's why the BIOS reads it as 2200+) that had disabled cache, or been disabled by any other means.
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Secondary rigs:
Core i7 2600K 3.4GHz @ 4.3GHz (Scythe Mugen2) / Mobo: Biostar TP67XE / 2x Inland Pro 120GB / GPU: HD5450 / Mem: 4x4GB DDR3-1600 G.Skill 8GBXL RipJawsX - 16GB total / PSU: Seasonic S12II 620W.
Core i3 540 3.06GHz @ 4.0GHz (Freezer 7 Pro) / Mobo: MSI H55M-ED55 / GPU: Integrated / Mem: 4x2GB DDR3-1600 G.Skill 4GBRL RipJaws - 8GB total / PSU: Antec 380W.
Core Temp - Accurate temperature monitor for Intel's Core/Core 2 and AMD64 processors
No, they meet at the crossbar, the System Request Queue. This in turn is connected to the HT links and the memory controller. So CPU-CPU cache snooping traffic never goes out to the HT links, like in a dual CPU system. This improves performance slightly.Originally Posted by The Coolest
Code:MC HT \ / SRQ / \ core1 core2
Opteron 165 CCBWE 0550UPMW@2.5 GHz 1.3 V 1GB / A64 3500+ 512M / A64 3500+ 512M / AXP 2500+@400FSB 1GB / AXP 2500+@400FSB 512M / AXP 1700+@333FSB 256M / AXP 1700+@300FSB 256M / Athlon 1150 384M / Ferrari 3000 AXP 2500+ laptop
Not exactly. An AMD dual core CPU will be able to *appear* as a single core with HT support. This is because some morons develop software for HyperThreading, but fail to spawn threads for multi-CPU. By appearing as a HT CPU an AMD dual core would be able to take advantage for HT-aware Dual-UNaware software.Originally Posted by LowRun
Opteron 165 CCBWE 0550UPMW@2.5 GHz 1.3 V 1GB / A64 3500+ 512M / A64 3500+ 512M / AXP 2500+@400FSB 1GB / AXP 2500+@400FSB 512M / AXP 1700+@333FSB 256M / AXP 1700+@300FSB 256M / Athlon 1150 384M / Ferrari 3000 AXP 2500+ laptop
Pjotr>> Yes you're right on the fact that there's System Request Queue between the cores and the memory controller. But what I wanted to say basically is that the CPUs are still two completely seperate cores.
HyperThreading is relatively old tech, dual core is relatively new, not all developers that were writing their programs for multi CPU support, never knew about Intel and AMD releasing multi-core CPUs in the future, so this feature allows older software to still have a noticable performance increase over running on a single core.
So I wouldn't call developers morons just because they didn't know about this.
Member of Overclockers.com Folding @ Home team
"<The_Coolest> you can't unwaste wasted CPU cycles" - Start FOLDing now!
Main rig:
AMD Ryzen 7 2700X / Mobo: Asrock Fatal1ty X470 / EVO 970 500GB + WD Blue 250GB + HDD / GPU: Dell RX 570 4GB / Mem: 2x16GB DDR4-3200 G.Skill 32GTZKW TridentZ - 32GB total / PSU: Seasonic Prime Ultra Gold 650W
Secondary rigs:
Core i7 2600K 3.4GHz @ 4.3GHz (Scythe Mugen2) / Mobo: Biostar TP67XE / 2x Inland Pro 120GB / GPU: HD5450 / Mem: 4x4GB DDR3-1600 G.Skill 8GBXL RipJawsX - 16GB total / PSU: Seasonic S12II 620W.
Core i3 540 3.06GHz @ 4.0GHz (Freezer 7 Pro) / Mobo: MSI H55M-ED55 / GPU: Integrated / Mem: 4x2GB DDR3-1600 G.Skill 4GBRL RipJaws - 8GB total / PSU: Antec 380W.
Core Temp - Accurate temperature monitor for Intel's Core/Core 2 and AMD64 processors
my question is, how can we overclocked it?
independent clock speed for each core, or just one for both? ummm I think 1, since it only have 1 mem controller and independent clock speed adjustment for each core is somewhat not logic
Originally Posted by c627627
To sell a part at 3.2, it needs to run at 3.4, at least, with no problems. This is known as a "guard band". I'm not sure 90nm will deliver that, especially by Q106.
It's also pure speculation, not really a "roadmap". Perhaps you should cite the evidence you have for each prediction on your website with a link to an explanation somewhere else on your site. That way, folks can distinguish between supposedly leaked roadmaps and speculation.
Oh, and I wouldn't rely on the Ediot for anything.
Well this is strange.Originally Posted by sxs112
If 4400 = 2 x (2.2GHz, 512K L2)
and (speculating) 4800 = 2 x (2.4GHz, 512K L2)
What the heck is 4600? Are they really going to release 2.3GHz cores? I guess that's possible, and perhaps makes some sense, even.
The alternative of: 4600 = 2 x (2.4, 512K L2), 4800 = 2 x (2.4, 1MB L2) is possible, but it doesn't make as much sense from the model number viewpoint.
Last edited by terrace215; 04-15-2005 at 09:24 AM.
Its very possible that this is what's going to happen:Originally Posted by terrace215
4200+ = 2.0GHz 2x512KB <-- Might not happen at all.
4400+ = 2.2GHz 2x512KB
4600+ = 2.4GHz 2x512KB
4800+ = 2.4GHz 2x1MB
I think that at least for now, both of the dual core CPUs are going to be called Toledo, as we don't have any other info on this.
Member of Overclockers.com Folding @ Home team
"<The_Coolest> you can't unwaste wasted CPU cycles" - Start FOLDing now!
Main rig:
AMD Ryzen 7 2700X / Mobo: Asrock Fatal1ty X470 / EVO 970 500GB + WD Blue 250GB + HDD / GPU: Dell RX 570 4GB / Mem: 2x16GB DDR4-3200 G.Skill 32GTZKW TridentZ - 32GB total / PSU: Seasonic Prime Ultra Gold 650W
Secondary rigs:
Core i7 2600K 3.4GHz @ 4.3GHz (Scythe Mugen2) / Mobo: Biostar TP67XE / 2x Inland Pro 120GB / GPU: HD5450 / Mem: 4x4GB DDR3-1600 G.Skill 8GBXL RipJawsX - 16GB total / PSU: Seasonic S12II 620W.
Core i3 540 3.06GHz @ 4.0GHz (Freezer 7 Pro) / Mobo: MSI H55M-ED55 / GPU: Integrated / Mem: 4x2GB DDR3-1600 G.Skill 4GBRL RipJaws - 8GB total / PSU: Antec 380W.
Core Temp - Accurate temperature monitor for Intel's Core/Core 2 and AMD64 processors
or, it could be that
4400+ = 2.2 GHz 2x512KB
4600+ = 2.2 Ghz 2x1MB
4800+ = 2.4 Ghz 2x512mb
and maybe a higher version later on with 2x1MB
This is analagous to the new Venice and San Diego cores w/
3500+ = 2.2 Ghz 512k
3700+ = 2.2 Ghz 1MB
3800+ = 2.4 Ghz 512k
Just MHO.
Not if you accept the italian site CPUZ shot, which featured:Originally Posted by Orthogonal
2.4GHz 2x1MB
It would be odd to be sampling a part this far in advance that wasn't going to be part of the launch (and thus probably the 2400+/4800+ A64 X2)
Last edited by terrace215; 04-15-2005 at 11:02 AM.
Of course I could be way off my rocker. If AMD is going to have the 4800+ as their new Flagship, it would most certainly have 2x1MB, if any at all have that much.
Yes. But HyperThreading is rather new, while dual core is over ten years old. It's not a new phenomenon.Originally Posted by The Coolest
I'm a developer and I would. Anyone programming threads based on number of CPUs *should* ask the system how many CPUs there are. They should *not* check if there is HT and forget to check for multiple CPUs. That's just stupid and I would slap my developers if they did that.So I wouldn't call developers morons just because they didn't know about this.
Opteron 165 CCBWE 0550UPMW@2.5 GHz 1.3 V 1GB / A64 3500+ 512M / A64 3500+ 512M / AXP 2500+@400FSB 1GB / AXP 2500+@400FSB 512M / AXP 1700+@333FSB 256M / AXP 1700+@300FSB 256M / Athlon 1150 384M / Ferrari 3000 AXP 2500+ laptop
Have you actually take the time to read how dual core works?
on the Intel side, which has HT, makes it a bit more complex:
First find out how many processors windows detects.
Then find out how many cores a single chip has.
Then find out how many virtual CPUs a single chip has.
Then find out which CPU is a virtual and which one is physical.
Build a list of which virtual CPU belongs to which physical, then make softare make the correct decision on what specific CPU to start a new thread....
Member of Overclockers.com Folding @ Home team
"<The_Coolest> you can't unwaste wasted CPU cycles" - Start FOLDing now!
Main rig:
AMD Ryzen 7 2700X / Mobo: Asrock Fatal1ty X470 / EVO 970 500GB + WD Blue 250GB + HDD / GPU: Dell RX 570 4GB / Mem: 2x16GB DDR4-3200 G.Skill 32GTZKW TridentZ - 32GB total / PSU: Seasonic Prime Ultra Gold 650W
Secondary rigs:
Core i7 2600K 3.4GHz @ 4.3GHz (Scythe Mugen2) / Mobo: Biostar TP67XE / 2x Inland Pro 120GB / GPU: HD5450 / Mem: 4x4GB DDR3-1600 G.Skill 8GBXL RipJawsX - 16GB total / PSU: Seasonic S12II 620W.
Core i3 540 3.06GHz @ 4.0GHz (Freezer 7 Pro) / Mobo: MSI H55M-ED55 / GPU: Integrated / Mem: 4x2GB DDR3-1600 G.Skill 4GBRL RipJaws - 8GB total / PSU: Antec 380W.
Core Temp - Accurate temperature monitor for Intel's Core/Core 2 and AMD64 processors
Except programmers are stereotypically lazy and will ask if the machine uses HT and not do any other checks. Which is obviously stupid/bad programming.
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if you program multithreaded, this shouldn't be a problem ?Originally Posted by Adamantine
compilers don't have to be adjusted either, do they ?or am i mistaking here ?
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