3800+ Venice Screenies (Post #1 = FAQ)

[s7e9h3n]

s7e9h3n if you could answer a quick Q for me: What's the stock vcore on these chips? 1.35? 1.4?

I've had boards in the past where the CPU-Z vcore reading and BIOS vcore reading didn't match up, and the CPU-Z reading is usuall much lower than the chosen setting in the BIOS, so I just wondered what vcore this chip is "supposed" to be running at by default. Thanks!

1.4 and are you sure you're just not experiencing vdroop?

[SAE]

Looking good so far, s7e9h3n

Cause it's working well under phase I am quite happy. I hope San Diego will do as well

BTW. Does your nick mean: Stephen?!?

[Ref]

I could do that, but I'd feel like I'm cheating

It is not considered as a cheat. A lot of people do it
And if you like to save the screenie in Kunaak's way(800x600 70%), I see no reason why you shouldn't take this screenie in a full quality.

[terrace215]

send that cpu to fugger maybe with his cascade can OC better

sure that cpu has strained SOI ???? i asked that and nobody answer me that

Yes, all 90nm parts have at least 1st gen strained silicon. These may (or may not, we don't know for sure yet) have second generation strained silicon, known as "DSL" (Dual Stress Liner).

[terrace215]

1.4 and are you sure you're just not experiencing vdroop?

Interesting that your CPU-Zs show 1.36v on a lot of the "stock" runs with air cooling. Are you deliberately undervolting slightly, or is that just happening despite being set to 1.4v in the BIOS?

[s7e9h3n]

Interesting that your CPU-Zs show 1.36v on a lot of the "stock" runs with air cooling. Are you deliberately undervolting slightly, or is that just happening despite being set to 1.4v in the BIOS?

Actually it's set to "default Cpu VID" (or something like that) in bios. 1.4 is default vcore for the venice. 1.36 is probably due to the motherboard undervolting a bit. Anybody wanna send me an Ultra-D to test with this cpu?

[bugeyes]

Anybody wanna send me an Ultra-D to test with this cpu?

It would cost less for postage if you sent me the cpu to test it in the dfi

[clockedOut]

Anybody wanna send me an Ultra-D to test with this cpu?

Yep, I have a complete retail box Ultra-D on the shelf.... you wanna send me the 3500 to test I will send you the DFI to test. LMK!!

:banana4:

[Stumpjumper5200]

Looks great!

It would be nice if AMD had a processor spec list like Intel's Sspec page on their site.

[perkam]

Check back a few pages. I think he's playing in this temperature range.

THanks conrad. OMG i posted only 2 hours ago and its 2 pages ahead Will check them out, thx for 2945 linky and OMG Conrad when'd u go mod ??? And lets some benchies in ur sig man !!!

I still wanna see some 3200+/3000+ benchies though before I'm completely conveniced .

Perkam

[Cpt Twitchy]

I'm loving the looks of this Venice core. Hopefully the rest are as awesome as this chip.

P.S. Are you going to test the 3500+ ?

[EMC2]

Very nicely done so far s7e9h3n

Would really like to see how the on-die mem controller does on that puppy

Maybe a "tightest timings TCCD, 4 DIMMs" with you FX and then with the Venice? (you could do it with 2 DIMMs, but the difference would probably show up more with 4) Pleeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeease.

[uwackme]

Thought part of the whole point of doing Venice/SanDiego was to implement the IBM version of Strained Silicon.... aka Super Strained Silicon. Along with SSE3 and better memory controller.

[EMC2]

Well, the cold bug appears gone, SSE3 was verified, so that leaves the mem controller As far as the SS question... something fixed the cold bug... and from the temps at volts, it appears they've cut down further on the leakage current

[bugeyes]

Well, the cold bug appears gone, SSE3 was verified, so that leaves the mem controller As far as the SS question... something fixed the cold bug... and from the temps at volts, it appears they've cut down further on the leakage current

dose the coldbug have any relationship to the memory controller?

[conrad.maranan]

THanks conrad. OMG i posted only 2 hours ago and its 2 pages ahead Will check them out, thx for 2945 linky and OMG Conrad when'd u go mod ??? And lets some benchies in ur sig man !!!

Yes. This thread is definitely popular. Since s7e9h3n first posted yesterday just after 1:00PM, this thread has been hit almost 38,000 times. Notice that the moment s7e9h3n puts up a screenshot, the posts start accumulating. Everyone has been waiting a long time for this.

As for moderating: I woke up yesterday and noticed Kazoo and friends at my door. FUGGER was in the background next to his pimped out Benz S600 sitting low on 24" Lowenharts wrapped in Pirelli P-Zero rubbers. chilly1 instructs him to pop the trunk and reaches for a Louis Vuitton duffle bag. They both commence to walk toward my door and post up next to Kazoo. chilly1 drops the bag and a fat stash of bundled cash makes its way out of the designer pouch. Kazoo hands me a badge that reads XtremeSystems Bodybag Crew and mumbles, "It's time to clean house." FUGGER looks me in the eye and says, "Make sure you do a good job." I put the badge on, shut the door, and log on to XS. The end.

[EMC2]

dose the coldbug have any relationship to the memory controller?

Unknown, but unlikely, could be an initialization problem most anywhere in the chip... I simply meant that the main Q left to be answered was what is the improvement in the mem controller on the Venice


--- Conrad ---

[mcnbns]

SERIOUSLY OT:

As for moderating: I woke up yesterday and noticed Kazoo and friends at my door. FUGGER was in the background next to his pimped out Benz S600 sitting low on 24" Lowenharts wrapped in Pirelli P-Zero rubbers. chilly1 instructs him to pop the trunk and reaches for a Louis Vuitton duffle bag. They both commence to walk toward my door and post up next to Kazoo. chilly1 drops the bag and a fat stash of bundled cash makes its way out of the designer pouch. Kazoo hands me a badge that reads XtremeSystems Bodybag Crew and mumbles, "It's time to clean house." FUGGER looks me in the eye and says, "Make sure you do a good job." I put the badge on, shut the door, and log on to XS. The end.

^Dude, that sounds so cool. No, seriously.


Uhh... lower speed rating Venice action? I wanna see a 3000+ hit 2.9GHz stable on air. Please? Anyone? AMD, are you there? April is so far away...

[perkam]

Uhh... lower speed rating Venice action? I wanna see a 3000+ hit 2.9GHz stable on air. Please? Anyone? AMD, are you there? April is so far away...

hmmm...2.9ghz would be 9x322 so someone with Venice + Gskill or Plat2 could do it, though it would be easier with a 3200's 10x multi : only 290 fsb required which many tccd can do.

Perkam

[TimoneX]

322x9 w/ a 166Mhz memory lock would suit me and my UTT sticks just fine.

[bachus_anonym]

hmmm...2.9ghz would be 9x322 so someone with Venice + Gskill or Plat2 could do it, though it would be easier with a 3200's 10x multi : only 290 fsb required which many tccd can do.

Perkam

I think you forgot about dividers here
322x9 divider166 = 263MHz --> good for some 6-2-2-2.0-1T BH-5 action
322x9 divider180 (on some boards, like DFI NF4) = 290MHz ---> great for some good clocking TCCD @ 7-3-3-2.5-1T

so, I think 2900MHz on 3000+ is still doable

[OjorisO]

I think you forgot about dividers here
322x9 divider166 = 263MHz --> good for some 6-2-2-2.0-1T BH-5 action
322x9 divider180 (on some boards, like DFI NF4) = 290MHz ---> great for some good clocking TCCD @ 7-3-3-2.5-1T

so, I think 2900MHz on 3000+ is still doable

But still 322 2.5-4-3-7 is doable on G.Skill memory (at least mine does 325) with OPB's (holy) timings

[Caper]

Which store is that? I can't find it...

http://www.sbs.o.se/default.asp?artnr=ADA3500BPBOX

[IvanAndreevich]

I expected more. However, first winchesters SUCKED and later ones got better So I think we can expect the same thing to happen here as well. Venice doesn't suck to begin with, so it will hopefully get close to 3.2 on AIR by Q3-Q4.

For non-believers remember FX-51 needing serious phase to get to 2.8 and some FX-53's getting there on air

[redgoo]

I would love to see the 3500+ results now.