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Thread: amd dual core preview

  1. #1
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    Toledo Bench?

    Got the link from [H], looks like a single benchmark of the Toledo.


    Looks Good, 2 X 2.4 G, socket 939, 1.4V, Thermaltake heatsink, nothing special. Damn near 2 X the performance!!

    Tranlated link:
    http://translate.google.com/translat...language_tools


    pfoot

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    Nice scores, but 512KB per core is not looking like what AMD promised. I hope we will have 1MB per core (2MB total). A promising performance. Thanks for this info pfoot.
    Last edited by agenda2005; 03-12-2005 at 09:56 AM.
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  3. #3
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    If you look at the Cpuz screenshot it shows 1024KB for CPU #1, that would mean cpu #2 also has 1024KB.

    Maybe someone can translate this better than Google:

    "On board is integrated two cache L2 distinguished, ciascuna in quantitative par to 1 Mbyte"

    pfoot

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    Is it still due out in Q3?
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  5. #5
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    Quote Originally Posted by pfoot
    If you look at the Cpuz screenshot it shows 1024KB for CPU #1, that would mean cpu #2 also has 1024KB.

    Maybe someone can translate this better than Google:

    "On board is integrated two cache L2 distinguished, ciascuna in quantitative par to 1 Mbyte"

    pfoot
    yeah, i was on the assumption it said two 1mb l2's.
    the fact that the screen shows 1mb for cpu #1 settles it for me.
    Got a fan over those memory sticks? No? Well get to it before you kill them

  6. #6
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    Looks really good. I just hope they put the new tech to good use
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    I think the two CPU share the same L2 cache, 512KB + 512KB = 1024KB. Correct me if I'm wrong. Does it mean each CPU cannot see the L2 cache of the other or was it CPU-Z that read it as been seperate?
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    Wow, I thought the dual core CPUs would require a unique mobo?!
    Laptop

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    I dont know what ciascuna means but the rest means quantity equal to 1M. More info and testing will answer those questions but my guess is shared 1M not 1M each. Hopefully I'm wrong.

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    Quote Originally Posted by agenda2005
    I think the two CPU share the same L2 cache
    It has always been my impression that each core has its own bank of cache that is specifically allocated to it. It is very possible that there will be an fx dual core with 1mb per core while the non-fx dual cores will have 512kb per core.
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    Quote Originally Posted by MikeMurphy
    Wow, I thought the dual core CPUs would require a unique mobo?!
    You just made me realize that they did say s939 didnt they!?!?
    Yeah, it was originally stated that dual core processors would require more pins to operate. However, this statement was made regarding Intel. Intel has to redesign their dual cores for a different socket because they are having to completely redesign the processor because Pentium 4 was not designed to be used with two cores. On the other hand, AMD created the athlon 64 with using two cores in mind. From the beginning the Athlon 64 has been designed to utilize the dual core, and the reason for the s754 to s939 socket change was most likely to accomodate the upcoming dual core processors.
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    This is K8, not intel shared L2 crap. Each core should have it's own L2 which should be accessible by other CPU through the HT bus.
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    Quote Originally Posted by CompGeek
    The US is the only country that doesn't use [nuclear weapons] to terrorize other countries. The US is based on Christian values, unlike any other country in the world. Granted we are straying from our Christian heritage, but we still have a freedom aimed diplomatic stance.

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    Quote Originally Posted by Jrocket
    It has always been my impression that each core has its own bank of cache that is specifically allocated to it. It is very possible that there will be an fx dual core with 1mb per core while the non-fx dual cores will have 512kb per core.
    You are right! However, that type of design will require a sophisticated memory controller which need to schedule data transfer between each CPU L2 and the correct bank, therefore a 1 or more cycle delay. They will also require a crossbar switch to access data from each others L2.
    Whereas a glueless design with shared L2 makes the work of the memory controller easier and no need for a crossbar. This is easier and more efficient, since A64 CPUs have an exclsive L2 cache.
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  14. #14
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    agenda2005
    You know this for sure? My memory must have faulted me then.
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    Quote Originally Posted by CompGeek
    The US is the only country that doesn't use [nuclear weapons] to terrorize other countries. The US is based on Christian values, unlike any other country in the world. Granted we are straying from our Christian heritage, but we still have a freedom aimed diplomatic stance.

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    Quote Originally Posted by IvanAndreevich
    agenda2005
    You know this for sure? My memory must have faulted me then.
    What does that suppose to me?
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  16. #16
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    nice! imagine what the FX is gonna be like

  17. #17
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    Quote Originally Posted by pfoot
    If you look at the Cpuz screenshot it shows 1024KB for CPU #1, that would mean cpu #2 also has 1024KB.

    Maybe someone can translate this better than Google:

    "On board is integrated two cache L2 distinguished, ciascuna in quantitative par to 1 Mbyte"

    pfoot
    ciascuna (ciascuno, really) means "each" in english

    1MB per core = 2MB total L2

  18. #18
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    Quote Originally Posted by agenda2005
    You are right! However, that type of design will require a sophisticated memory controller which need to schedule data transfer between each CPU L2 and the correct bank, therefore a 1 or more cycle delay. They will also require a crossbar switch to access data from each others L2.
    Whereas a glueless design with shared L2 makes the work of the memory controller easier and no need for a crossbar. This is easier and more efficient, since A64 CPUs have an exclsive L2 cache.
    I see what you mean, but if they were to share the cache then we would most likely not see as high of speed because we would only have one inlet to the processor instead of two seperate banks pulling from the hyper transport link. You would run into one core waiting on the other. I think the plan is to take the information from the hyper transport link split it into two even groups to be processed by the two seperate banks and cores in order decrease traffic. As far as the crossover bar is concerned, you wouldnt necessarily have to use it. Using it would only allow either core to correct a recent mistake, and this is not something that needs to be switched to the other core. Instead you could keep the raw data seperately allocated and merge the two afterwords, much like SLI.
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  19. #19
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    so does the dual core cpu physically have 1mb or 2mb? amds roadmap says 2mb
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  20. #20
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    1MB per core AFAIK
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    Quote Originally Posted by CompGeek
    The US is the only country that doesn't use [nuclear weapons] to terrorize other countries. The US is based on Christian values, unlike any other country in the world. Granted we are straying from our Christian heritage, but we still have a freedom aimed diplomatic stance.

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  22. #22
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    woah! Looks awsome!
    Any idea of when these things are due to be released?

    Alec

  23. #23
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    not to rain on your parade or anything saaya, but this is old news http://www.xtremesystems.org/forums/...ad.php?t=55889

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    ah, sorry i must have missed it

    will merge the threads

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    the results are sweet! the 250 runs at 2.4ghz as well, right?
    so the dual core 2.4ghz is even faster than the dual opteron rig?

    now its important to know if the dual opteron had numa or not though, but i guess not.

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