Complete A64 Memory Divider Table

[OSKAR_WU]

Complete A64 Memory Divider Table

Ps : It may not be 100% correct

[boshi]

umm... ok...

cool

[Karnivore]

Thanks Oskar, nice bit of info :thumbsup:

[OSKAR_WU]

Originally posted by OSKAR_WU
Complete A64 Memory Divider Table

Ps : It may not be 100% correct

Any problem from this table ?

[texuspete00]

Nice to see you again OSKAR. This will come in useful for my yuletide A64 system.

[CodeRed]

Better off presenting a table of memory dividers.

125 MHz is actually 117 MHz AFAIK
No idea about the 143 MHz setting.
in goes in steps of 1/12

[OSKAR_WU]

Originally posted by CodeRed
Better off presenting a table of memory dividers.

125 MHz is actually 117 MHz AFAIK
No idea about the 143 MHz setting.
in goes in steps of 1/12

I think you know DRAM frequency we set in A64 register is " Upper limit " of DRAM speed ...

A64 memory controller will automatically choose a smallest interger divider(>4) to generate the DRAM clock from Core Frequency , and the DRAM clock will not be faster than the uppder limit ...

Using an oscilloscope and check all the multiplier from 4~12 with the same register setting in A64 ...

What I got are 200/183/166/150/143/125/100 may be the upper limit of DRAM speed when you set correspoding register setting in A64 ...

Here is the divider table I got after using an oscilloscope to check the possible upper limit of DRAM clock ...

What I can not be sure is the exact frequency besides 200/166.67/133.34/100 ...

[tictac]

wow....

[tritium]

That looks nice, but since I do not have an A64 yet can you please explain the chart. Memory speed, HTT setting , CPU ratio etc....

Thanks

[Dissolved]

Tagged..

[Edward Ng]

Sorry, but I need to ask the obvious question...

Any way you can find out or tell us what happens to the RAM Divider for DRAM Freq. over 200 in BIOS? For example, if I use DRAM Freq. 225, 250, 275 or 300?

Thank you for any information you can provide, and furthermore, thank you so much for your efforts, Oskar. Your LP nF3 is a true marvel of modern engineering!

-Ed

[craig588]

You can't use a devidor less than your multiplier.

[Edward Ng]

Okay, suddenly I understand...

I was thinking of the LDT setting, not the RAM ratio.

Gotcha'; thanx.

[saaya]

wow....

ditto!

thx a lot oskar!

[craig588]

Yeah, I love this divider table.

[Çhrist0ph]

where did the divider table go? Can someone post it again?

[Learn]

where did the divider table go? Can someone post it again?

*.png8 139KB & 155KB

[papatsonis]

it simpler if u don want to remember tables.

u multiply the (HTT/ram) ratio -inverse of ram:htt ratio in the bioses- with the
cpu multiplier , and u aproximate to its closer bigger integer.that's ur memory divider,then u divide ur cpu mhz by this divider..

example if multi is 8 ,HTT=240(=>cpu=1920MHZ) and divider "ram:htt" is 5:6 , u multiply 8*(6/5)=9.6 , then approximate to the bigger closer integer =.. 10 and divide the cpu clock by ths number ...=> ram clock is 1920/10=192mhz

of course if u choose a half multi , the bios "approximates" it to the closest integer(bigger)

[FrozenGPU]

it simpler if u don want to remember tables.

u multiply the (HTT/ram) ratio -inverse of ram:htt ratio in the bioses- with the
cpu multiplier , and u aproximate to its closer bigger integer.that's ur memory divider,then u divide ur cpu mhz by this divider..

example if multi is 8 ,HTT=240(=>cpu=1920MHZ) and divider "ram:htt" is 5:6 , u multiply 8*(6/5)=9.6 , then approximate to the bigger closer integer =.. 10 and divide the cpu clock by ths number ...=> ram clock is 1920/10=192mhz

of course if u choose a half multi , the bios "approximates" it to the closest integer(bigger)

Wow, that IS a lot simpler.

[FoxTrottZero]

I'm new here and to OCing... but I have a theory about pushing the Hz and Voltage on the system:
I think that these tables indicate it off the bat, but what I imagine is that it really helps to keep the frequencies in as efficient a synch rate as possible...
Looks like... a 4Ghz system would be most stable if one were to use RAM of as compatable a frequency... something like 400Mhz
That way, the clock pulses have a pretty good chance of interlacing properly.

From what I understand, AMD's FSB controls the RAM directly from the CPU, so it would make sense then to make sure that you can run compatible RAM. Seems like the system would be better of say at 4Ghz then at 4.1 with 400mhz ram in terms of stability.
Now Raw speed... that's another thing
Just an idea, I really have no expertise on this.

BS?

[p4z1f1st]

oskar, or somebody else:

could you tell me the "interval" with which you calculated that all?

because, i want to extend the table with clocks like 217/233/250/266/275/283/300MHz

[p4z1f1st]

ok, got it:

multiplier * your wanted FSB(HTT)-clock / wished divider (f.e. - 166 for the 6:5-divider or 133 for the 3:2-divider and so on) = a real-count

you have to "up-round" the result - so, if it's 13,2 you have to say, it's 14 - if 12,6 it's 13, if 12,1 it's 13, too

so, then:

CPU-Clock / result of the first calculation = REAL RAM-CLOCK


one full example:

13 * 200 / 166 = 15,66 ---> = 16

2600 / 16 = 162,5MHz

[saaya]

isnt it funny that it goes to 5ghz cpu speed but only 200mhz memory speed? ^^

[papatsonis]

i have some ''objections'' tο the above table

it needs to be clear enough, what exact every ratio is,e.g. 166/200=5/6 , but for the not common ones (183,143) , is more ..misty

the 183/200 what should be? 183.3333333/200 which means 11/12 ??? ,should be 9/10 as dfi says in the bios??? , or 10/11 ???
From the table , we can find some multis that are in the ''edge'' to change for different ratios (9/10, 10/11, 11/12) so the rounding could be different ,and IF , we assume the table is correct we might find the right one.

--from now on will be LONg post

for 10x multi(CPU) 10/9 gives 11,1111-> 12x ram multi
11/10 gives 11 -> 11x
12/11 gives 10.9-> 11x

for 19x , 10/9 =21.1111-> 22x
11/10=20.9 -> 21x
12/11=20.73->21x

for 20x , 10/9=22.2 ->23x
11/10=22->22x
12/11=21.81->22x

for 21x , 10/9 =23.3->24x
11/10=23.1->24x
12/11=22.9->23x

for 22x , 10/9=24.4->25x
11/10=24.2->25x
12/11=24->24x

so.. from the table and the calculated ram mlutis (for cpu 10x,19x,20x) we can easily see, that the 10/9 is unacceptable, so 11/10 or 12/11

but...for 21x multi =4200MHZ clock , for 183mhz ram setting ,the table says 182.61MHZ =..23x ram multi as for 11/12 ratio

and for 22x =4400mhz >> , >> 176mhz, as for 11/10 ratio..!!?? whats happens here??of course IMO , the correct ratio is 11/12 as for 183.33333333/200

doing the same thoughts in propotion for the 143mhz divider , i think -and seems to be confirmed the 5/7 ratio ,

2 more observations.. :

1)all the mem dividers for half multi dividers, are ''calculated"-oscilloscoped from the above table, like the half multis do exist, but... we all think that they are just a trick to give more flexibility.example from the table : 6.5x cpu multi , 5/6 ratio (should be =rounded to 7*1.2=8.4=..9x ram multi) ,but it gives 6.5x1.2=7.8=..8x ram ratio.Also note that for 1:1 setting the half multis are normally up-rounded .. so may that mean that the half multis DO EXIST when not using 1:1 htt:ram setting???
2) the cpu multies <5x seems to be emulated using 5x multi , as a consequense the 4x multi 1:1 gives only 160mhz!!

[tictac]

0.5multi bug....

Oskar wu can you fix it?