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Thread: WPCREDIT tweaks for the A64

  1. #76
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    Originally posted by HKPolice
    BTW, the 2T command rate doesn't seem to work with my C0 stepping A64... I try to enable it, and it just goes back to disable after pressing set. I don't think this is a bug with your program though since I tried modifying it with wcpredit before, and it did the same thing. Any reason for this?
    2T is only supported by CG stepping and above

  2. #77
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    Nice Job.

    Works with my setup.

  3. #78
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    Originally posted by cpulloverclock
    excellent

    what are the best timings and settings for

    max asynch latency
    read preamble
    idle cycle limit
    dynamic idle cycle counter
    max async latency .. the lower the better, but I cant run below 6ns at max FSB

    read preamble ... doesnt seem to do much, 4ns is good
    idle cycle limit ... 16 clocks (irrelevant with dynamic enabled)
    dynamic ... enabled

    also set read write queue bypass & bypass max to their max values

  4. #79
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    what about the tref? which is the most aggressive timing? i assume lower the ns the aggressive it is?

  5. #80
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    Originally posted by Ragnarok
    what about the tref? which is the most aggressive timing? i assume lower the ns the aggressive it is?
    Tref is the DRAM refresh rate. Refresh doesnt happen that often so it doesnt affect performance to badly. The less frequency refresh rates are best for performance, but it wont make any noticeable difference

  6. #81
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    nice!!! JOB!! CODERED question though what would be the best settings for a A64 3000 newcastle and a K8N PRO. with OCZ EB pc3500 ?? Shroomalistic what settings u using since we seem to have the same set-up

  7. #82
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    Originally posted by CodeRed
    max async latency .. the lower the better, but I cant run below 6ns at max FSB

    read preamble ... doesnt seem to do much, 4ns is good
    idle cycle limit ... 16 clocks (irrelevant with dynamic enabled)
    dynamic ... enabled

    also set read write queue bypass & bypass max to their max values
    I'm running at 5ns
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  8. #83
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    Originally posted by cpulloverclock
    I'm running at 5ns
    Wow, I expect to see some great superpi and pifast scores then.

    Have you tried 3dmark .. it would be interesting to see what are the best timings for that. Maybe it will be different for car, lobby & drago. Even can change mem ratio for each test

  9. #84
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    Just tried using the 183Mhz setting, and it works, but CPU-Z doesn't show the actual clock of the ram... Is there another prog that will?

  10. #85
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    Nice Tweaker, CodeRed.




    They will fall at his feet....... But eBay @ZZHOLE still ripped me off!

  11. #86
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    there is a black screen when I move the write cas latency timing, and you?

    beta cpu-z 1.23 special S775
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  12. #87
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    where 1 can download that

  13. #88
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    Originally posted by Duronbird
    where 1 can download that
    nowhere
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  14. #89
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    Originally posted by cpulloverclock
    there is a black screen when I move the write cas latency timing, and you?

    beta cpu-z 1.23 special S775
    Yes, same for me.

    Will the newest CPU-Z report all the tiiming values?

    I can give the author the info he will need to do this if required.

  15. #90
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    Originally posted by CodeRed
    Yes, same for me.

    Will the newest CPU-Z report all the tiiming values?

    I can give the author the info he will need to do this if required.
    yes you can for the trcd, trDRAM

    Franck has some problems with this version and the I925, 915 about the frequency memory, he doesnt know how to recover it

    if somebody can help us saving a dump with different ratios and to send that to franck : cpuz@cpuid.org

    example of this problem :


    Last edited by cpulloverclock; 06-23-2004 at 02:49 PM.
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  16. #91
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    The app you provided CR works fine on my 8KDA3+ and C0 3400+ Full stepping info is somewhere in a thread over on OCAU

    One thing I noticed though, it kills MBM5 if you have it running at the same time. Nothing to be worried about though
    Last edited by fxr91; 06-23-2004 at 05:01 PM.
    3D01 - 29649
    3D03 - 13055
    AM3 - 72618

  17. #92
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    Originally posted by fxr91
    [B]

    One thing I noticed though, it kills MBM5 if you have it running at the same time.
    speedfan also.

  18. #93
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    Originally posted by CodeRed
    Yes, same for me.

    Will the newest CPU-Z report all the tiiming values?

    I can give the author the info he will need to do this if required.
    and for the 32 byte granularity? a freeze when I put disable (enable by default)
    I love XS

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  19. #94
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    Originally posted by cpulloverclock
    and for the 32 byte granularity? a freeze when I put disable (enable by default)
    Same again for me too.

    I might remove the options that cause freezes in the next release. No point in having them if they dont work.

    tRCD is obtained from bits 14-12 of the DRAM Timing Register (Low). Bus 0, Device 24, Function 2. It's encoded as follows:

    000b = reserved (probably 0 clocks :o )
    001b = reserved (probably 1 clock)
    010b = 2 clocks
    011b = 3 clocks
    100b = 4 clocks
    101b = 5 clocks
    110b = 6 clocks
    111b = reserved (probably 7 clocks)

    Thats straight from the AMD specs.


    tDRAM? Whats this, its not in the AMD specs? Does it go by another name perhaps?

    EDIT: never mind about tDRAM I misread it .. tRDRAM

  20. #95
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    Originally posted by CodeRed
    Same again for me too.

    I might remove the options that cause freezes in the next release. No point in having them if they dont work.

    tRCD is obtained from bits 14-12 of the DRAM Timing Register (Low). Bus 0, Device 24, Function 2. It's encoded as follows:

    000b = reserved (probably 0 clocks :o )
    001b = reserved (probably 1 clock)
    010b = 2 clocks
    011b = 3 clocks
    100b = 4 clocks
    101b = 5 clocks
    110b = 6 clocks
    111b = reserved (probably 7 clocks)

    Thats straight from the AMD specs.


    tDRAM? Whats this, its not in the AMD specs? Does it go by another name perhaps?

    EDIT: never mind about tDRAM I misread it .. tRDRAM
    ok I'm blind
    Last edited by cpulloverclock; 06-24-2004 at 04:46 AM.
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  21. #96
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    Originally posted by fxr91
    The app you provided CR works fine on my 8KDA3+ and C0 3400+ Full stepping info is somewhere in a thread over on OCAU

    One thing I noticed though, it kills MBM5 if you have it running at the same time. Nothing to be worried about though
    Does it crash when A64Tweaker starts up or when you hit the "Set" button?

    @//mAr, same question


    My suspicion is that the io.dll module I use to access the PCI config space registers is doing something weird with the I/O Permission Map .. probably doing something stupid like setting exclusive access. This dll doesnt have the facility to customise the permission map, I might drop the author a line on this one.

  22. #97
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    Works fine on mi 3400+ C0 CAAOC

    Wich are the best Tras, Trc and idle timer for A64? I'm actually running at 284 1:1 3-4-4-10-10-16 2'8V (CPUZ Info)
    || Core 2 Quad QX6850 ES @ 3.5Ghz 1.35V || Thermalright Ultra 120 || Asus P5K3 Deluxe || Gskill F3-12800CL7D-2GBHZ
    || XFX 8800GTX || Dell 2005FPW 20" || Ultra X-Pro 750W LE || 3 x WD 320GB SD + 1 x Hitachi 500GB

  23. #98
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    My BH5 likes
    Tras = 5
    Trc=8
    Idle Timer = 16

    But considering your current timings I doubt your mem will take it ... try it anyway.

  24. #99
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    For all settings, the lower the better, except for Tras, anandtech did an article about it, and they say a setting of 10 is best for A64 platforms. In Sisandra, I notice no difference between 5 and 10, but in memtest86, 10 does yield about a 30MB/s increase.

  25. #100
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    ohh my god this proggy makes my computers a lot faster !!!! runs smooth like butter keep working on the new version guys!!!

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