WPCREDIT tweaks for the A64

[thomase]

Can someone take a look at section 3.3.13 of the BIOS and Kernel Developer's Guide? This register has some Read-Only bits which specify the valid settings (there are 16 available) for LDT Link Frequency. Are any of the "reserved" settings available? If so, what LDT multipliers do they correspond to? Are there any "hidden" settings in addition to 1x, 2x, 3x, 4x, and 5x? Even if additional settings are available, it may be the case that chipset support is needed in order to get it to work. Both sides need to communicate at the same rate.

EDIT: I found the following in the HyperTransport 2.0 specification doc.

Table 54. Link Frequency Bit Field Encoding
Link Frequency Encoding Transmitter Clock Frequency (MHz)
0000 200 (default)
0001 300
0010 400
0011 500
0100 600
0101 800
0110 1000
0111 1200
1000 1400
1001 1600*
1010 to 1110 Reserved
1111 Vendor-Specific
Note: Electrical requirements of the link above 1400MHz have not been fully specified at this time.

I guess there are no in-between multipliers other than 1.5x and 2.5x. The "Vendor-Specific" setting is 100 MHz (from the BIOS and Kernel Developer's Guide).