[rumour] AMD "Zen 2" IPC 29 Percent Higher than "Zen"

[Nelly]

AMD reportedly put out its IPC (instructions per clock) performance guidance for its upcoming "Zen 2" micro-architecture in a version of its Next Horizon investor meeting, and the numbers are staggering. The next-generation CPU architecture provides a massive 29 percent IPC uplift over the original "Zen" architecture. While not developed for the enterprise segment, the stopgap "Zen+" architecture brought about 3-5 percent IPC uplifts over "Zen" on the backs of faster on-die caches and improved Precision Boost algorithms. "Zen 2" is being developed for the 7 nm silicon fabrication process, and on the "Rome" MCM, is part of the 8-core chiplets that aren't subdivided into CCX (8 cores per CCX).

According to Expreview, AMD conducted DKERN + RSA test for integer and floating point units, to arrive at a performance index of 4.53, compared to 3.5 of first-generation Zen, which is a 29.4 percent IPC uplift (loosely interchangeable with single-core performance). "Zen 2" goes a step beyond "Zen+," with its designers turning their attention to critical components that contribute significantly toward IPC - the core's front-end, and the number-crunching machinery, FPU. The front-end of "Zen" and "Zen+" cores are believed to be refinements of previous-generation architectures such as "Excavator." Zen 2 gets a brand-new front-end that's better optimized to distribute and collect workloads between the various on-die components of the core. The number-crunching machinery gets bolstered by 256-bit FPUs, and generally wider execution pipelines and windows. These come together yielding the IPC uplift. "Zen 2" will get its first commercial outing with AMD's 2nd generation EPYC "Rome" 64-core enterprise processors.

Update Nov 14: AMD has issued the following statement regarding these claims:

As we demonstrated at our Next Horizon event last week, our next-generation AMD EPYC server processor based on the new 'Zen 2' core delivers significant performance improvements as a result of both architectural advances and 7nm process technology. Some news media interpreted a 'Zen 2' comment in the press release footnotes to be a specific IPC uplift claim. The data in the footnote represented the performance improvement in a microbenchmark for a specific financial services workload which benefits from both integer and floating point performance improvements and is not intended to quantify the IPC increase a user should expect to see across a wide range of applications. We will provide additional details on 'Zen 2' IPC improvements, and more importantly how the combination of our next-generation architecture and advanced 7nm process technology deliver more performance per socket, when the products launch.

Source: Expreview, TechPowerUp

[AliG]

There's absolutely no way Zen 2 has a 29% increase across the board. I'll buy big increases in specific areas, especially AVX, but the architecture is just an evolution. It'd be content with a 10% increase to be frank.

[Charles Wirth]

IPC increase across the board is possible, they are making advancements at a better pace now with Zen.

[Charles Wirth]

AVX and other instructions is where a lot of the architecture performance increases come from, AMD does have a dominant decrypt instruction sets now with Zen.

[madcho]

I just hope it's coming soon

[zanzabar]

There's absolutely no way Zen 2 has a 29% increase across the board. I'll buy big increases in specific areas, especially AVX, but the architecture is just an evolution. It'd be content with a 10% increase to be frank.

They get a huge penalty using all cores on epic and TR. I would not be surprised if fixing the fabric to work properly with JDEC memory speeds would do that much.

[AliG]

According to Expreview, AMD conducted DKERN + RSA test for integer and floating point units, to arrive at a performance index of 4.53, compared to 3.5 of first-generation Zen, which is a 29.4 percent IPC uplift (loosely interchangeable with single-core performance).

The data in the footnote represented the performance improvement in a microbenchmark for a specific financial services workload which benefits from both integer and floating point performance improvements and is not intended to quantify the IPC increase a user should expect to see across a wide range of applications.

I don't see any evidence that they were running identical systems here. As far as we know part of the performance increase could be due to the improved manufacturing process increasing clocks. Furthermore, AMD themselves is trying to reduce expectations. Zen+ already had a decent increase due to better cache and clockspeed, wouldn't be surprised if AMD built off that along with an optimized pipeline could get you to the 29% increase in specific scenarios.

Call me skeptical, but I want to see a trusted report before I believe it. AMD always brags when they have something real - let them do a public demonstration and I'll buy in.