3D NAND flash revolutionized flash storage as it used the third dimension (height) to stack multiple NAND flash layers, resulting in infinitesimally smaller footprint and reduced costs. SK Hynix believes that a "4-dimensional" NAND flash package is possible. Don't worry, such a stack doesn't look like a tesseract. Conventional 3D NAND flash relies on stacks of charge-trap flash (CTF) cells spatially located alongside its periphery block (which is responsible for wiring out each of the layers of the CTF stack). On a 2-D plane you'd be spending substrate real-estate on both the CTF and periphery block.
SK Hynix believes that the periphery block can be stacked along with the CTF stack, with microscopic vias wiring up the stack along the periphery, reducing the footprint of each cell stack. 4D stacking will also allow for greater number of CTF stacks per cell. Just to be clear, we're talking about stacks of cell and not stacks of NAND flash dies. The V5 cell-stack in SK Hynix's design entails 4 cells and periphery blocks sandwiched. The first implementation of this technology is a 96-layer 4D NAND flash chip with 512 Gb of capacity and TLC (3 bits per cell) density, although the technology is ready for QLC cells. This 512 Gb chip will begin sampling by the end of 2018, and the company is already working on a 1 Tb chip for 2019.
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