DARPA, the US Defence Advanced Research Projects Agency, has selected the research teams that will be working on creating the next wave of US semiconductor design innovation. The governmental body reckons that it is far too difficult for small entities, as well as the Department of Defence (DoD), to leverage the high performance technology needed to design complex circuits for defence applications. Thus it is funding a programme, with $1.5 billion over five years, to address this key problem.
The programme is dubbed the DARPA Electronics Resurgence Initiative (ERI) and research teams from academia, commercial industry, and the defence industrial base have been selected to address SoC design complexity and cost barriers. ERI is split into two initiatives; the Intelligent Design of Electronic Assets (IDEA) program and the Posh Open Source Hardware (POSH) program. IDEA and POSH will create a software-based, completely automated physical layout generator and an open-source intellectual property (IP) ecosystem. It is hopes that it will facilitate a 24-hour design cycle for DoD hardware systems, shorten upgrade cycles, and enable the proliferation of custom commercial and DoD-specific SoCs.
IDEA researchers will apply machine learning methodologies to continuously evolve and improve the performance of a layout generator for digital circuits, ICs, SiPs and PCBs. It will essentially eliminate the DoD's resource and expertise gap associated with custom electronic hardware design.
POSH will concentrate on SoC design research. The aim is to create an open source SoC design and verification ecosystem that will enable the cost-effective design of ultra-complex SoCs. Andreas Olofsson, the Microsystems Technology Office program manager leading IDEA and POSH, said that "Through POSH, we hope to eliminate the need to start from scratch with every new design, creating a verified foundation to build from while providing deeper assurance to users based on the open source inspection process."
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