[News/Rumor] Intel Can Make a 20-core "Skylake-X" SKU if it Wants to

[StyM]

https://www.techpowerup.com/235977/i...if-it-wants-to

Intel "Skylake-X" silicon is a monolithic vast processor die built on the 14 nm process. The company carved out 6-core, 8-core, 10-core SKUs in its Core i7 and Core i9 X-series socket LGA2066 HEDT SKUs on this chip, and is scheduled to launch 12-core, 14-core, 16-core, and 18-core SKUs by the end of 2017. Intel can even carve out a 20-core SKU from this chip, if it wants to. Die-shots of "Skylake-X" surfaced when the company launched the first Core X processors, along the sidelines of the 2017 Computex.

A quick glance of the "Skylake-X" die-shot revealed in Intel's presentation for the Core X family, reveals that the chip has 20 physical CPU cores. It also has its 28,160 KB (27.5 MB) of L3 cache greatly segmented into bits of 1408 KB (1.375 MB). With "Skylake-X," Intel has replaced its rather archaic "ringbus" interconnect with the new Mesh topology that cuts down latencies between distant components on the die.

[AliG]

I don't really see the technical challenge in simply scaling up 2 more cores with the Skylake-X architecture. The new intercore cache + memory management system is very flexible.

The only reason Intel hasn't done it is AMD doesn't offer an 18 core desktop variant of their own (yet). My guess is it's only a matter of time before you see the full Epyc chips anyways.

[Sparky]

Or, it is just smoke and mirrors "we can too!" because of feeling some heat.

[Tenknics]

This is not news.

Intel can do A LOT of things and it doesn't. That's their business model. Hence a mainstream 6c dropping in 2017. smh

[Particle]

Two of the cores TPU highlighted appear to actually be memory controllers. Seems to be an 18-core die.

[StAndrew]

Two of the cores TPU highlighted appear to actually be memory controllers. Seems to be an 18-core die.

You might be right, the article no longer exists.

[kromosto]

If he wants intel's CEO can wipe the floor with AMD's CEO...

[iddqd]

My CEO could totally beat up your CEO!!!

[zanzabar]

You might be right, the article no longer exists.

since intel has an e5 and e7 28 core die does it matter what they brand as an i7? i dont see them putting out a $20k i7, but they could.

[kromosto]

My CEO could totally beat up your CEO!!!

if your CEO wants it of course, isn't it...

[StAndrew]

If he wants intel's CEO can wipe the floor with AMD's CEO...

Intel might have the performance advantage but AMD has the innovative advantage. Part of the reason Intel's processors are priced so high is because they have to be. Monolithic and complex cores such as the Xeon and i9's are very expensive to make. AMD is mass producing one core and through "infinity fabric" is able to "glue" them together and scale from 4 cores/4 threads, to 32 core/64 threads. On one core.

Intel would have to take costs out of hide just to compete with AMD's initial release price.

[Tenknics]

Intel might have the performance advantage but AMD has the innovative advantage. Part of the reason Intel's processors are priced so high is because they have to be. Monolithic and complex cores such as the Xeon and i9's are very expensive to make. AMD is mass producing one core and through "infinity fabric" is able to "glue" them together and scale from 4 cores/4 threads, to 32 core/64 threads. One one core.

Intel would have to take costs out of hide just to compete with AMD's initial release price.

Intel has been doing what you described as a unique AMD advantage, since Nehalem.




AMD doesn't make a 1-core product. Nor do they manufacture single cores at a time and then "glue them together" to make greater core counts. AMD's base for Zen is the 4 core complex (CCX) and it scales from there. It's no different from what Intel has been doing for the last decade with the Core i architecture.

[StAndrew]

I disagree.

[AliG]

Tenknics is right, Intel developed the SandyBridge ringbus for that purpose, and greatly improved the interconnect scalability with Skylake-X.

AMD is using 1 (superb) chip because they have to. If AMD had Intel's R&D budget, their chips would be monolithic. Instead, they found a way to scale up without as much development cost - albeit losing some efficiency. Their L3 is WAYYYYY slower than Intel's because of the way they had to do the interconnect. Any small task that needs L3 calls is significantly faster on Skylake-X.

[StAndrew]

Tenknics is right, Intel developed the SandyBridge ringbus for that purpose, and greatly improved the interconnect scalability with Skylake-X.

AMD is using 1 (superb) chip because they have to. If AMD had Intel's R&D budget, their chips would be monolithic. Instead, they found a way to scale up without as much development cost - albeit losing some efficiency. Their L3 is WAYYYYY slower than Intel's because of the way they had to do the interconnect. Any small task that needs L3 calls is significantly faster on Skylake-X.

AMDs solution is not the same as intels. And i9 is different from Nehalem.

The L3 is comparable to Intels except when a core on one CCX has to access the L3 in the other CCX. AMDs solution allows them to do what has never been done before and order a ton of CPUs and 'glueing' them together to scale from 4 to 32 cores. Intel will never be able to compete in pricing even if they wanted to.

[qcmadness]

AMDs solution is not the same as intels. And i9 is diffarent from Nehalem.

The L3 is comparable to Intels except when a core on one CCX has to access the L3 in the other CCX. AMDs solution allows them to do what has never been done before and order a ton of CPUs and 'glueing' them together to scale from 4 to 32 cores. Intel will never be able to compete in pricing even if they wanted to.

In fact Intel still have lower costs due to in-house processes and higher volume, but they don't want to lower their profit margins.

[qcmadness]

Tenknics is right, Intel developed the SandyBridge ringbus for that purpose, and greatly improved the interconnect scalability with Skylake-X.

AMD is using 1 (superb) chip because they have to. If AMD had Intel's R&D budget, their chips would be monolithic. Instead, they found a way to scale up without as much development cost - albeit losing some efficiency. Their L3 is WAYYYYY slower than Intel's because of the way they had to do the interconnect. Any small task that needs L3 calls is significantly faster on Skylake-X.

The costs of working in a new chip design at bleeding-edge processes (aka sub 14nm/16nm) has skyrocketed compared with 20nm / 28nm. Now the manufacturing cycle-time is more than 4 months. Masks are north of $100 millions. And the validation and testing takes much more time.

I don't think AMD has the volume and manpower to work on multiple dies as Intel (this year: Kaby-lake 3 dies, Cannonlake 1-2 dies, Skylake-X 3 dies, etc.).

[Tenknics]

AMDs solution is not the same as intels. And i9 is diffarent from Nehalem.

The L3 is comparable to Intels except when a core on one CCX has to access the L3 in the other CCX. AMDs solution allows them to do what has never been done before and order a ton of CPUs and 'glueing' them together to scale from 4 to 32 cores. Intel will never be able to compete in pricing even if they wanted to.

I think your info is a little misguided. Intel has been scaling 4-32 cores long before AMD did. And also Intel is very capable of lowering prices, if they wanted to. Their margins are more important to them then anything.


What are you basing this information on? Do you work for Intel? I'm confused.

[xlink]

As stated, the CPU has 18 physical cores and two core-sized memory controllers.

I made this mistake myself and cited it a handful of times elsewhere thinking I was clever for counting... I was wrong.

[AliG]

The L3 is comparable to Intels except when a core on one CCX has to access the L3 in the other CCX. AMDs solution allows them to do what has never been done before and order a ton of CPUs and 'glueing' them together to scale from 4 to 32 cores. Intel will never be able to compete in pricing even if they wanted to.

Lolwut? That makes literally no sense. The CPU has to make an L3 cache call when the data is too large to be stored on L2 or needs to be shared with another core. End of story. AMD's solution just adds latency (at the benefit of lowering cost).

I really think you should take a basic class on chip design. I'm sure you can find plenty of good ones on coursera.

[StAndrew]

I think your info is a little misguided. Intel has been scaling 4-32 cores long before AMD did. And also Intel is very capable of lowering prices, if they wanted to. Their margins are more important to them then anything.

What are you basing this information on? Do you work for Intel? I'm confused.

Are they ordering just one CPU core / silicon and scaling it from i3 to their top Xeon processor? Did I miss something?

Ok, you got me. It's just an opinion. But its not pulled out of my butt; it's pretty simple ergonomics. Ordering just one piece of silicon and scaling it from Ryzen 3 all the way up to the 32 core Epyc server chips is a major accomplishment in manufacturing efficiency.

But since you challenge my credibility without so much as giving credence to yours, I'm curious why you think a: the i9 shares the same "modularity" as the i7, b: why you think Intel has enough 'margin' to lower prices to compete with AMD, and lastly c: why you think AMD's margins are so tight they don't have the ability to lower prices further.

Maybe you're right. I'd rather be wrong and learn something than getting internet cookies for being right. But at least make a case and not base your tenability on the lack of mine.

Lolwut? That makes literally no sense. The CPU has to make an L3 cache call when the data is too large to be stored on L2 or needs to be shared with another core. End of story. AMD's solution just adds latency (at the benefit of lowering cost).

I really think you should take a basic class on chip design. I'm sure you can find plenty of good ones on coursera.

I'm not exactly saying your wrong, but the higher L3 latencies that are generally discussed are due to the CCX design. But yes, even local cache latency is slower than Intel's, which is nothing new. But it isn't so bad as to be a huge performance deficit until the core has to use the infinity fabric to access the L3 on a different CCX.

https://www.techpowerup.com/231268/a...cx-compromises

However, on AMD's Ryzen 1800X, latency times are a wholly different beast. Everything is fine in the L1 and L2 caches (32 KB and 512 KB, respectively). However, when moving towards the 1800X's 16 MB L3 cache, the behavior is completely different. Up to 4 MB cache utilization, we see an expected increase in latency; however, latency goes through the roof way before the chip's 16 MB of L3 cache is completely filled. This clearly derives from AMD's Ryzen modularity, with each CCX complex (made up of 4 cores and 8 MB L3 cache, besides all the other duplicated logic) being able to access only 8 MB of L3 cache at any point in time.

The difference in access speeds between 4 MB and 8 MB workloads can be explained through AMD's own admission that Ryzen's core design incurs in different access times depending on which parts of the L3 cache are accessed by the CCX. The fact that this memory is "mostly exclusive" - which means that other information may be stored on it that's not of immediate use to the task at hand - can be responsible for some memory accesses on its own. Since the L3 cache is essentially a victim cache, meaning that it is filled with the information that isn't able to fit onto the chips' L1 or L2 cache levels, this would mean that each CCX can only access up to 8 MB of L3 cache if any given workload uses no more than 4 cores from a given CCX. However, even if we were to distribute workload in-between two different cores from each CCX, so as to be able to access the entirety of the 1800X's 16 MB cache... we'd still be somewhat constrained by the inter-CCX bandwidth achieved by AMD's Data Fabric interconnect... 22 GB/s, which is much lower than the L3 cache's 175 GB/s - and even lower than RAM bandwidth. That the Data Fabric interconnect also has to carry data from AMD's IO Hub PCIe lanes also potentially interferes with the (already meagre) available bandwidth.

[AliG]

I'm not exactly saying your wrong, but the higher L3 latencies that are generally discussed are due to the CCX design. But yes, even local cache latency is slower than Intel's, which is nothing new. But it isn't so bad as to be a huge performance deficit until the core has to use the infinity fabric to access the L3 on a different CCX.

https://www.techpowerup.com/231268/a...cx-compromises

You just proved my point. That article literally validates everything I claimed about Intel's design scaling better. CCX = design cost save, not special innovation that's unique to AMD.

[StAndrew]

You just proved my point. That article literally validates everything I claimed about Intel's design scaling better. CCX = design cost save, not special innovation that's unique to AMD.

Well then you need to be more clear in the future? I'm not sure how you are saying I'm wrong because we are agreeing...?

Either way, the concept isn't unique in and of itself but what is unique is that for the first time that I can remember, an entire CPU lineup, from budget to mainstream to HEDT to server is based off one building block. Costs savings, I'm sure, are a big deal.

To clarify what I was trying to point out IRT L3 Latency, it is comparable to Intel in the traditional sense. Latency from the core to L3. "Except when a core on one CCX has to access the L3 in the other CCX."

The following statement was a little misleading for me... Especially when you consider "any small task." L3 latency doesn't suffer infinity fabric or system memory penalties until the 8MB local L3 is saturated so I would assume "small tasks" on a Ryzen processor won't suffer, compared to on an Intel processor, from L3 latency.

Their L3 is WAYYYYY slower than Intel's because of the way they had to do the interconnect. Any small task that needs L3 calls is significantly faster on Skylake-X

Also, statements like

Lolwut

reduces my ability to take seriously anything further typed by about 100%.

[chew*]

I know one thing intel can not do even if they wanted to.

Stop me from being an AMD enthusiast.

[StyM]

all i want for Christmas is 20c @ 899 ...