AMD's advantage with Summit Ridge and Naples is that they are using a strong interconnect to allow them to manufacture multiple relatively-small dice to scale up core counts and eliminate yield problems. Intel's solution to-date is always to increase the die size or at least increase transistor count per die. If you look at what is going on with Skylake-X, keeping everything on-die isn't a perfect solution, especially since Intel has been forced to (or simply chosen to) abandon their internal ring bus interconnects in favor of their new mesh topology which is screwing with cache and memory performance. Of course we also have to look at the "bolt on" solution they have chosen for AVX-512 as a culprit there as well, but that is a different matter entirely.
Anyway Intel has their own version of "glue" in the works so they can go to the same basic strategy, alleviating the need to increase die size (or maintain die size with new node shrinks) in order to increase core counts. I forget what they're calling it.
edit: Intel calls it EMIB
Last edited by drmrlordx; 08-13-2017 at 02:38 PM.
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