The biggest architectural change is an increase in ALU width from 16 pipelines per cluster to 32. Each cluster also doubles up from four bilinear samples per clock to eight. Anandtech's Ryan Smith wrote a fairly detailed overview of the new architecture, which can be read here. Smith notes that while each cluster is substantially wider, the new design may be somewhat less flexible and that the increased capabilities per cluster may be offset somewhat by a decreased cluster count when Furian is integrated into SoCs.
The design house says that when compared to Series 7XT Plus parts built on the same manufacturing process, Furian should be good for a 33% improvement in GFLOPS density, an 80% increase in fillrate density, and an improvement of at least 70% in what it called "gaming density," claiming that the performance improvement in real world applications is "better than the sum of the parts."
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