AMD Prank King 2016, FAIL!!

[qcmadness]

Sure it is, but we've already seen quad core ES (allegedly existing), and AMD has positioned itself to sell a lot of these if the performance is good.
I don't think AMD would want to sell 8c/16t ~200-250mm dies when they could sell 4c/8t dies at half the area and greatly increase margins on the lower end of the addressable market. What would it cost AMD to create the 4 core die, another $100m? It seems to me like that would be the smartest choice if they are expecting several billion USD in revenue.

Expensive wafers on an expensive process, fitting twice as many dies on a wafer reaps rewards with high volume. Not everyone is going to want a $300-600 8c/16t, I think a lot of people will also be interested in a $150-250 4c/8t.

The cost is upwards of $300M.

[BeepBeep2]

The cost is upwards of $300M.

You think so, or know so? The cost of bringing any new CPU / SoC to market has been quoted by some random sources in between $80-300m. AMD has a budget of about ~$275m / quarter in R&D over the past 3 years, which I would assume is split between Radeon GPU and CPU divisions. They released Tonga, Fiji, Polaris 10 + 11, Excavatorv1 (Carrizo), Excavatorv2 (Bristol Ridge), Puma, Puma+ over 28nm/14nm and all sorts of packages, and dies, while also working on Zen and Vega during this time, not to mention whatever costs were related to Semi-Custom development.

The production masks for 14nm I also highly doubt costs more than lower $x0M's, though nobody knows what the WSA w/ GloFo is in detail.

I don't think it would cost AMD $300m to cut Zen from an 8-core layout to 4-core layout, most of that R&D and design is already done at that point, though it would have to be routed and packaged differently. (I would assume that had been done already since a CCX = 4 cores)

Another reason it would absolutely blow my mind if it took anywhere close to an extra $300M to bring a 4-core die / SKU to market: the financials math does not seem to add up. "Selling and general administrative" was $482m for FY2015, and R&D was only $987m.


(Also: Though completely off the current topic, this is my favorite post by JF-AMD here considering the direction AMD is going with Zen: http://www.xtremesystems.org/forums/...=1#post4700221)

[qcmadness]

You think so, or know so? The cost of bringing any new CPU / SoC to market has been quoted by some random sources in between $80-300m. AMD has a budget of about ~$275m / quarter in R&D over the past 3 years, which I would assume is split between Radeon GPU and CPU divisions. They released Tonga, Fiji, Polaris 10 + 11, Excavatorv1 (Carrizo), Excavatorv2 (Bristol Ridge), Puma, Puma+ over 28nm/14nm and all sorts of packages, and dies, while also working on Zen and Vega during this time, not to mention whatever costs were related to Semi-Custom development.

The production masks for 14nm I also highly doubt costs more than lower $x0M's, though nobody knows what the WSA w/ GloFo is in detail.

I don't think it would cost AMD $300m to cut Zen from an 8-core layout to 4-core layout, most of that R&D and design is already done at that point, though it would have to be routed and packaged differently. (I would assume that had been done already since a CCX = 4 cores)

Another reason it would absolutely blow my mind if it took anywhere close to an extra $300M to bring a 4-core die / SKU to market: the financials math does not seem to add up. "Selling and general administrative" was $482m for FY2015, and R&D was only $987m.


(Also: Though completely off the current topic, this is my favorite post by JF-AMD here considering the direction AMD is going with Zen: http://www.xtremesystems.org/forums/...=1#post4700221)

http://semiengineering.com/finfet-ro...than-expected/

[drmrlordx]

BTW there is a binary code published in the CanardPC article mentioned in the OP:

http://imgur.com/a/iTP6f

The binary code apparently translates to something like ZenOC=5G

[vario]

BTW there is a binary code published in the CanardPC article mentioned in the OP:

http://imgur.com/a/iTP6f

The binary code apparently translates to something like ZenOC=5G

One thing i dont understand is, if this review was not authorised by AMD, then why "hide" this info in some cryptic binary code message, instead of just doing the OC and some tests ?

[BeepBeep2]

http://semiengineering.com/finfet-ro...than-expected/

Yes, but that article says absolutely nothing to counter my points. Just because 14nm FF was delayed doesn't mean prices are 20x higher than the node it replaced...

BTW there is a binary code published in the CanardPC article mentioned in the OP:

http://imgur.com/a/iTP6f

The binary code apparently translates to something like ZenOC=5G

01011010011001010110111001001111010000110100000001 0000010110100101110010001111010011010101000111

ZenOC@Air=5G

A march 2016 magazine also had "Intel = AMD GPU" on the same page

[FlanK3r]

I think, OC around the 5 GHz will be LN2, air +- 4.2 to 4.3 GHz (similar as Haswell-E/ BW-E)

[Kai Robinson]

What a ridiculous thread title. Does OP realise that this isn't 4chan?

[StAndrew]

I think, OC around the 5 GHz will be LN2, air +- 4.2 to 4.3 GHz (similar as Haswell-E/ BW-E)

I think Intel and AMD measure TDP differently but I would think with original TDP of 95W for the Ryzen, it should be very good overclocker if they can ever sort out the silicon. I'm actually a bit surprised AMD is limiting their chip to 95W unless they plan to release a high clocked 140W "Black" or "FX" chip later (or are keeping it under wraps until launch). Although, smaller nodes will generally lead to much more voltage leaking when overvolting/clocking; I'll be surprised if we see 5Ghz but won't be too surprised to see something between 4.0-4.7Ghz...

I'm still sticking with my original prediction that Ryzen won't be a ground breaking clocker or performer at release and AMD will have a revised stepping or even new chip with a better silicon late 2017 or early 2018.

[SinOfLiberty]

4.3ghz cinabench run before it crashes, in this yes, def clockable.