New Middleware Technology Quadruples SSD Speed

[felix_w]

I bumped on this :

A Japanese research team developed a technology to drastically improve the writing speed, power efficiency and cycling capability (product life) of a storage device based on NAND flash memory (SSD).

.... The new method forms a middleware layer called "LBA (logical block address) scrambler" between the file system (OS) and FTL. The LBA scrambler works in conjunction with the FTL and converts the logical addresses of data being written to reduce the effect of fragmentation.


...In a simulation, the research team confirmed that the new technology improves the writing speed of SSD by up to 300% and reduces power consumption by up to 60% and the number of write/erase cycles by up to 55%, increasing product life. Because, with the new method, it is not necessary to make any changes to NAND flash memory, and the method is completed within the middleware, it can be applied to existing SSDs as it is.

Source : Tech-On


Let's hope this will result in even better performing SSD's in the following years...

[zalbard]

"By up to"

I guess we will see what real-world gains are like. Hopefully this does not get patented by a single drive manufacturer.

[fgw]

Because, with the new method, it is not necessary to make any changes to NAND flash memory, and the method is completed within the middleware, it can be applied to existing SSDs as it is.

have read this news somewhere, but missed this important piece of text!

looks like this technology can also be used on current ssd's by firmwareupdate ...

[Nizzen]

I want lower latency, not higher seq read and write. My Areca 1883 takes care of that with 8x ssds.

Io extreme slc latency for sas/sata 256GB +ssds ftw

[felix_w]

...or an ACARD 9010 DDR4 (unicorn edition) for you then!!!!

[lowfat]

This will become irrelevant as drives transition away from AHCI to NVMe.

[zalbard]

This will become irrelevant as drives transition away from AHCI to NVMe.

Huh? The proposed improvement does not depend on a particular drive interface.

[Iconyu]

It sounds great for enterprise and HEDT users, but it's useless for the mainstream right now, if you place these drives on PCIe, too many users have only 16x lanes to play with.

[lowfat]

Huh? The proposed improvement does not depend on a particular drive interface.

New drives will not be SATA/AHCI. So a middleware program that affects the way a SATA drive writes to the drive will be useless. NVMe is written from the ground up so there is no need for software to overcome limitations of a 10+ year old interface that was designed around a 20 year old interface.

[NEOAethyr]

New drives will not be SATA/AHCI. So a middleware program that affects the way a SATA drive writes to the drive will be useless. NVMe is written from the ground up so there is no need for software to overcome limitations of a 10+ year old interface that was designed around a 20 year old interface.

Yeah but this isn't really about the interface form the computer to the drive, it's the drive's nand controller programming that this is about.
Think of it like a new ver of trim that improves reliability and speed.

[lowfat]

Yeah but this isn't really about the interface form the computer to the drive, it's the drive's nand controller programming that this is about.
Think of it like a new ver of trim that improves reliability and speed.

NVMe isn't a physical interface. It is the way the controllers are designed. No longer using SATA (ACHI) commands. AHCI was designed for mechanical drives. NVMe is designed ground up for solid state storage. In theory there should actually no longer TRIM commands sent from the OS.

http://en.wikipedia.org/wiki/NVM_Express

[mattkosem]

New drives will not be SATA/AHCI. So a middleware program that affects the way a SATA drive writes to the drive will be useless. NVMe is written from the ground up so there is no need for software to overcome limitations of a 10+ year old interface that was designed around a 20 year old interface.

This technology doesn't appear, as far as I'm reading here, to be specific to any host bus. Which facet of this technology are you tying to that specific implementation, and for what reason? This appears to reside directly below the filesystem and I'm not seeing any indication that, with the move to NVM Express, filesystems will no longer address blocks of data (that is, after all, their bread and butter). That being the case, why would a technology (or, in my opinion, more accurately "technique") that adds efficiency to the flushing of modified blocks to storage medium not still be effective? NVM express will add huge increases to bandwidth, and add a host of other efficiency related improvements, but that doesn't necessarily negate other write-efficiency-related gains. The point where this technology seems to reside (which is a bit vague based on the flow charts and descriptions provided) seems to be an area that could impact any storage medium (SAS, SD, etc.). It seems to be a method of making legacy filesystems more friendly for flash medium.

Am I missing something here, or is there a more detailed/technical analysis of this technique somewhere that you found?

--Matt

[iddqd]

You actually want fragmentation for these things, to maximaze parallelism gains. Also, I'm pretty sure most SSD controllers already do quite a lot of this intentional fragmentation, and logical-to-physical addressing translation. They actually do quite a lot more twiddling with your data than just that, even.

[NEOAethyr]

@lowfat

I really couldn't make anything out of that wiki page for the hardware layer.
All I got out of it is that it's similar to m2, which does have a nand controller...

I'm gonna get WAY off topic hear lol, but I soon hope the day comes soon when we just plug rom in ram slots and map it as physical memory.
No reason why the bios can't load straight off a physical ram address...
Stick a little arm chip there and use it to boot the bios without a cpu and ram...
Nand controllers are cpu's anyways..., I don't know what specific chips they use but I guess that can do some things like a cpu.
I watched a hacking speech on them it was kinda interesting.

Edit...
Then again what the heck am I thinking, it doesn't matter, it's all software anyways...

[mattkosem]

Nand controllers are cpu's anyways..., I don't know what specific chips they use but I guess that can do some things like a cpu.

I think most storage drives (mechanical or SSD) have multi-core arm-based controllers, in modern times at any rate.

--Matt

[STEvil]

only WD Black advertises multicore controllers, though technically I havent looked recently.

[DeathReborn]

only WD Black advertises multicore controllers, though technically I havent looked recently.

Samsung's ?MHz MCX (830), 300Mhz MDX (840, 840 Pro) & 400MHz MEX (840 Evo) are all 3 Core ARM R4 based controller chips.

[mattkosem]

Samsung's ?MHz MCX (830), 300Mhz MDX (840, 840 Pro) & 400MHz MEX (840 Evo) are all 3 Core ARM R4 based controller chips.

Yep, and Indilinx, LAMD, Marvel, etc. The list goes on. Even my old C300s had multiple arm cores, and they're 4 years old at this point. The Seagate drives in my HTPC have dual core CPUs too. Arm claims that greater than 50% of the hard drives shipped worldwide include arm cores.

--Matt