Ivy Bridge Temperatures Could Be Linked To TIM Inside Integrated Heatspreader: Report

[Mafio]

i don't know if ivy is super hot because of new tri-gate transistor, because of crappy thermal compound or what else.
the only thing i know is that take off the IHS from a CPU which have IHS and DIE not soldered together ALWAYS gives some kind of improvement.

[Lightman]

Guys, to me all of you are right, but only as a collective!

Small part of a problem with temp. is TIM but it's really tiny. I wager a guess that removing IHS and mounting air cooler directly on die will yield 5C-10C difference which maybe give you extra 50MHz headroom.
Big part of temperature problem is, as Hondacity says, leakage. New 22nm tri-gate process is designed primarily for low power designs. It simply has different scaling characteristics to typical high performance process and voltage increases are killing efficiency much quicker than on older processes.

Only hope is that Intel will still want to refine 22nm node towards higher clocks, but they hit all targets first time around and without competition there isn't much incentive for them to do so.

Similar thing happened at Glo-Fo when they moved from 45nm to 32nm. New process seems to be power hog at high frequencies but is very competitive power wise with mid to low clocks.

[zalbard]

The problem here is w/mK (thermal conductivity) in which case Indigo Xtreme is 2x better than the leading TIM.

I think liquid metal is still better. Especially on very flat surfaces...

Intel thermal specs does mention about TIM applied on IB
http://www.intel.com/content/www/us/...ket-guide.html

Thermal Interface Material != Thermal Paste. Could be Solder as well. Although using thermal paste would explain a lot of heat issues...

[Warwian]

Intel thermal specs does mention about TIM applied on IB
http://www.intel.com/content/www/us/...ket-guide.html

The Intel Thermal Guide for Sandy Bridge also mentions the use of TIM between the Core and IHS.

http://www.intel.com/content/www/us/...ket-guide.html

In fact, the same picture are used for both guides so they don't really tell us that much.

[wez]

You could put cookies in between the core/IHS and it would be a TIM. Its not the material that decides what it is, but the usage.

[thegoatman]

Not exactly true. For example, the chocolate in your cookies would act as a thermal insulator, not a thermal interface.

Reference: http://www.hardwaresecrets.com/artic...ry-2012/1490/5

Yes, they did test a CPU under chocolate. And butter. And toothpaste. Among other things.

[dejo]

Not exactly true. For example, the chocolate in your cookies would act as a thermal insulator, not a thermal interface.

Reference: http://www.hardwaresecrets.com/artic...ry-2012/1490/5

Yes, they did test a CPU under chocolate. And butter. And toothpaste. Among other things.

and american cheese, that was funny.

[imog]

http://kingpincooling.com/forum/show...1107#post21107

[Hornet331]

Guys, to me all of you are right, but only as a collective!

Small part of a problem with temp. is TIM but it's really tiny. I wager a guess that removing IHS and mounting air cooler directly on die will yield 5C-10C difference which maybe give you extra 50MHz headroom.
Big part of temperature problem is, as Hondacity says, leakage. New 22nm tri-gate process is designed primarily for low power designs. It simply has different scaling characteristics to typical high performance process and voltage increases are killing efficiency much quicker than on older processes.

Only hope is that Intel will still want to refine 22nm node towards higher clocks, but they hit all targets first time around and without competition there isn't much incentive for them to do so.

Similar thing happened at Glo-Fo when they moved from 45nm to 32nm. New process seems to be power hog at high frequencies but is very competitive power wise with mid to low clocks.

Bingo, at least some guys still use logic.

The TIM between the IHS and the die plays a pretty minor roll. We are already at freaking 22nm and the lower we go the more we will see energy consumption or for that matter leakage and therefore temperature will increase with raising voltage. I bet we will see the same topic again once intel introduces there 16nm process..

[Stukov]

Bingo, at least some guys still use logic.

The TIM between the IHS and the die plays a pretty minor roll. We are already at freaking 22nm and the lower we go the more we will see energy consumption or for that matter leakage and therefore temperature will increase with raising voltage. I bet we will see the same topic again once intel introduces there 16nm process..

Yes and no. Sure we will see more leakage without newer technology that prevents leakage (due to thinner walls), but that assumes we won't have newer technology to prevent leakage. It does make logical sense knowing that thinner walls = more leakage, but that doesn't mean it is 100% causation to the heat IB has while being overclocked. As you said it could be because of both TIM/IHS issue and thinner walls, but you can't know the extent of either without taking the IHS off both SB and IB and apply the same heatsink/thermal component and test at similar voltages and compare the heat. Even then, depending on your results you may still not know if it is simply the thinner walls or if there is a manufacturing issue that only presents itself when the chip is pushed. SB may simply use a different baking method that results in less yields but better numbers and with no AMD pressure Intel may have just went with a method that gives them great yields but below than average numbers (cuz even these are enough to push back any AMD pressure). In the end, it could be combination of all these factors. Without testing or some inside info, we probably won't know.

[Buckeye]

I have just a few questions about all this.

What CPU was this he took the lid off ? ES or Retail ?
Lower end non K versions might use this as they are not ment to be overclocked, but has a K version had the lid removed ?

If the CPU's are running in the designed frequency range and they stay at designed TDP then there is np I would think. K version however are different, but we all know they are ment to be overclocked so better cooling used would be the norm anyway.

Also consider that using solder might be giving them troubles with lead use so they switched to a different tim to be more environmentally friendly.

[hokiealumnus]

What CPU was this he took the lid off ? ES or Retail ?
Lower end non K versions might use this as they are not ment to be overclocked, but has a K version had the lid removed ?

It was an ES i7 3770K. Shammy's might have been retail; currently waiting on a response in that thread.

If the CPU's are running in the designed frequency range and they stay at designed TDP then there is np I would think. K version however are different, but we all know they are ment to be overclocked so better cooling used would be the norm anyway.

That's correct. It would just be unfortunate for overclockers as you are unable to cool as effectively without solder.

No TIM has the thermal properties of solder unless they have come up with something not even close to what is commercially avaliable. Shin Etsu - 6.0W/mK. Indigo Extreme is the best on the market that I can find, claiming > 20W/mK. Intel's patent doesn't rate the conductivity, but solder is capable of well north of 80+W/mK.

Also consider that using solder might be giving them troubles with lead use so they switched to a different tim to be more environmentally friendly.

There isn't lead in their solder to my knowledge. Their patent states gold & tin @ 80/20 ratios (See 7th page down, column 3, 2nd full paragraph.)

[Aberration]

Maybe gold is just getting too expensive.

[BeepBeep2]

It was an ES i7 3770K. Shammy's might have been retail; currently waiting on a response in that thread.

That's correct. It would just be unfortunate for overclockers as you are unable to cool as effectively without solder.

No TIM has the thermal properties of solder unless they have come up with something not even close to what is commercially avaliable. Shin Etsu - 6.0W/mK. Indigo Extreme is the best on the market that I can find, claiming > 20W/mK. Intel's patent doesn't rate the conductivity, but solder is capable of well north of 80+W/mK.

There isn't lead in their solder to my knowledge. Their patent states gold & tin @ 80/20 ratios (See 7th page down, column 3, 2nd full paragraph.)

PK-1 is rated 10.2W/mK, MX-4 being rated 8.5 W/mK...
Then the difference between Indigo Xtreme and PK-1 being less than 2c in most scenarios...I don't think solder has to do completely with the "up to 20c" difference. The heat is concentrated within a denser area.

Matt was a little conservative with his 5 W/mK, and on top of that you have to realize what an IHS is there for, to enlarge the surface area before the heat is transferred by the heatsink.

I'm not sure why the patent says it is an 80/20 Au/Ag solder, but it is well known that the solder is predominately indium/tin based (52/48%) with a melting point of 118c and conductivity of 40W/mK, low enough to ensure safe reflow -
So is AMD's method...

http://www.intel.com/technology/itj/...s/5-solder.htm
http://www.google.com/url?sa=t&rct=j...-9ev18uygQ8uHQ

[BeepBeep2]

But I thought that was the stuff intel stopped using in the early 2000's (my link shows a "4.0 w/mK" TIM replaced by solder)

I'm pretty sure they use the 52/48% indium/tin combination with melting point of 118c -
Page 18
http://www.intel.com/content/dam/doc...cket-guide.pdf

[hatter]

Tech Report asked Intel but did not get a decent answer

Curious, we asked Intel about the interface between the Ivy Bridge die and the heat spreader. Intel has confirmed to TR that Ivy uses a "different package thermal technology" than Sandy Bridge. The firm stopped short of answering our questions about why the change was made and how the thermal transfer properties of the two materials compare. However, Intel claims the combination of the new interface materialand Ivy's higher thermal density is responsible for the higher temperatures users are observing with overclocked CPUs.

http://techreport.com/discussions.x/22859

[M.Beier]

I have just a few questions about all this.

What CPU was this he took the lid off ? ES or Retail ?
Lower end non K versions might use this as they are not ment to be overclocked, but has a K version had the lid removed ?

If the CPU's are running in the designed frequency range and they stay at designed TDP then there is np I would think. K version however are different, but we all know they are ment to be overclocked so better cooling used would be the norm anyway.

Also consider that using solder might be giving them troubles with lead use so they switched to a different tim to be more environmentally friendly.

According to my facebook, it has been done as well with i7-3770K today
By a Swedish dude

[sin0822]

just watch this video if you are wondering about why leakage and temps are so high:
http://www.youtube.com/watch?v=bm6Sc...ayer_embedded#!

p1t1 took it off a dead ES. He showed the picture like a few weeks ago, if not longer.

[hokiealumnus]

M.Beier, if the Sweedish dude you're referring to is the one directed from this post @ OCN, it reportedly says this (I don't know the language so I have to trust the poster):

"I changed the paste between the IHS and die, but the IHS HAS to be in place, or else the brittle processor pcb does not make proper contact with the socket pins. This operation helped a little, now it doesn't throttle so easily near 4.9Ghz. I got +50Mhz, so there is NO BENEFIT. So, DO NOT destroy your cpu's."

The reason he had to put the IHS back on is b/c of his water block's mounting design. Since all he was doing was replacing the TIM with a different TIM and re-installing the IHS, that exercise was futile. The XT is designed to put a pre-set amount of pressure on a CPU with an IHS. Removing that changed the potential pressure to be applied. The CPU wouldn't make proper contact because the pressure applied by the XT on the CPU isn't even strong enough to hold it in. That's why he had to put the IHS back on, which defeated the purpose.

Anyway, no one is saying that de-lidding the CPU will drastically decrease temperatures. The whole point is that Intel went with TIM and not solder, the latter of which would result in better temperatures because of the much higher thermal conductivity of solder between the die and IHS.

[DilTech]

PK-1 is rated 10.2W/mK, MX-4 being rated 8.5 W/mK...
Then the difference between Indigo Xtreme and PK-1 being less than 2c in most scenarios...I don't think solder has to do completely with the "up to 20c" difference. The heat is concentrated within a denser area.

Matt was a little conservative with his 5 W/mK, and on top of that you have to realize what an IHS is there for, to enlarge the surface area before the heat is transferred by the heatsink.

I'm not sure why the patent says it is an 80/20 Au/Ag solder, but it is well known that the solder is predominately indium/tin based (52/48%) with a melting point of 118c and conductivity of 40W/mK, low enough to ensure safe reflow -
So is AMD's method...

http://www.intel.com/technology/itj/...s/5-solder.htm
http://www.google.com/url?sa=t&rct=j...-9ev18uygQ8uHQ

If the difference between 10.2 and 8.5 is around 2c for such a small difference in W/mK, that's ~1:1 gain... Now jump from 10 to 40 (although I think 40 is actually a conservative estimate since solder can go a LOT higher than 40)... That could definitely be responsible for a vast majority of the heat issue when you combine it with the smaller surface area. Basically, you have a smaller area and WORSE thermal conductivity...

[rge]

And to add to what DilTech said, you cant go by manufactures data bulk conductivity for tim, some are as accurate as fan specs. There is bulk thermal conductivity, interface resistance, and most importantly non-standard testing. For example AS5 I think lists their tim as 8 w/mK, yet has been tested on actual cpus to be less than 1 w/mk by both NREL and other reputable testers. Shin itsu and Dow was consistently measured as highest at ~ 4 w/mK on more than one study, and they accurately list their as such. Found NREL, page 9,http://www.nrel.gov/docs/fy08osti/42972.pdf . Any manufacturer that lists TIM paste as performing higher than 6 w/mK, better come with independent proof, not saying its not out there, but certainly havent seen any proof yet. phase change/indigo materials/thermoplastics aside.

I will try to find that power point slide from intel I posted somewhere in this forum couple years ago, but their solder attach was updated in past few years, and melting point was 150C, thermal cond ~80 w/mk.

But Hatters post from Tech report, to me, pretty much sums it up... However, Intel claims the combination of the new interface material and Ivy's higher thermal density is responsible for the higher temperatures users are observing with overclocked CPUs.

And for those that dont think TIM matters with large resistance changes.....

At 100 W/cm2 heat dissipation in the die, the maximum junction temperature (TJ,max) decreases by 16°C when TIM resistance decreases from 100 to 8 mm2K/W

http://www1.eere.energy.gov/vehicles...narumanchi.pdf slide 15

[M.Beier]

M.Beier, if the Sweedish dude you're referring to is the one directed from this post @ OCN, it reportedly says this (I don't know the language so I have to trust the poster):

The reason he had to put the IHS back on is b/c of his water block's mounting design. Since all he was doing was replacing the TIM with a different TIM and re-installing the IHS, that exercise was futile. The XT is designed to put a pre-set amount of pressure on a CPU with an IHS. Removing that changed the potential pressure to be applied. The CPU wouldn't make proper contact because the pressure applied by the XT on the CPU isn't even strong enough to hold it in. That's why he had to put the IHS back on, which defeated the purpose.

Anyway, no one is saying that de-lidding the CPU will drastically decrease temperatures. The whole point is that Intel went with TIM and not solder, the latter of which would result in better temperatures because of the much higher thermal conductivity of solder between the die and IHS.

Nope that is a Fin guy.

Not sure if the Swedish bloke has a profile on XS but here is the pic

[hokiealumnus]

Thanks; that's a nice pic. Do you if his was retail? From Intel's comments, it probably doesn't matter, but it never hurts to get both.

[BeepBeep2]

If the difference between 10.2 and 8.5 is around 2c for such a small difference in W/mK, that's ~1:1 gain... Now jump from 10 to 40 (although I think 40 is actually a conservative estimate since solder can go a LOT higher than 40)... That could definitely be responsible for a vast majority of the heat issue when you combine it with the smaller surface area. Basically, you have a smaller area and WORSE thermal conductivity...

What exactly is the estimate...that number is from Indium corp. about their own 52/48 indium/tin solder? It wasn't a guess...

I said the difference between 20 and 10.2 was around 2c. (Indigo Xtreme vs high end TIM) Not 10.2 and 8.5.

So you'd be looking at under 8c difference on an overclocked CPU, not 20...

[blindbox]

I'd wager properly soldering the IHS on with special equipment is more costly than dabbing a few drops of crappy TIM on there and securing the IHS.

Not too hard to do it by hand actually. Take some measurements, scratch the IHS to show where the chip should be when IHS is popped in, put the fluxless solder, mount the CPU to the IHS, with the IHS on the bottom. Let it cool somehow.

The extra cost for carving that IHS to show where the location might add a little to the cost, and of course, the fluxless solder they use is much more expensive than TIM.

It's not expensive but rather, relatively expensive.