Ivy Bridge Temperatures Could Be Linked To TIM Inside Integrated Heatspreader: Report

[imog]

And if so, ES and Retail chips could use different TIMs.
This needs further investigation and perhaps an official reply from Intel as well.

Intel's reply is pending, regarding an answer to that question specifically. I had to tell them I was writing it in order to get a real response, beyond "secret sauce". And since I told them I was writing it, I figured I should go ahead and actually write it.

To the others, the forum post was tangible proof that TIM paste may be used on IB. The review temps and everyone spouting off BS about power density without any proof is what the article was written from. The result will be an actual answer for everyone, hopefully.

The image was pt1t's, used with permission.

[thegoatman]

So if the chips ship like this... who wants to be the first to write an Ivy Bridge Pop-topping guide?

[Hondacity]

Intel with its vast resources is questioned. seriously? lol

Several forum members say/question "Intel doesn't know sh*t about installing IHS"

Intel is the 2nd biggest spender in R&D. Intel's R&D budget: $7.71 billion

**

My take on the design, Ivy is indeed hot. You just can't push it higher compared to Sandy on air. Even if you push it it wont be stable, you're forced to settle with the lower clocks but this will prolong life for the cpu. Intel WIN, users do not necessarily lose. there is sandy bridge.

as for extreme overclockers... the cpu scales with cold.

as for regular overclockers.. come join the subzero guys

[imog]

Intel with its vast resources is questioned. seriously? lol

Please state clearly what you mean?

Is it hondacity's "official position" that Intel used TIM paste because they believe it to be a superior solution for Ivy Bridge?

I need you to state specifically what it is you are saying, rather than chastise what other people are saying. That way when you are wrong, we can chastise you. lol

[Hondacity]

ivy isn't designed like sandy.

its core characteristics that influence the overclocking potential.

the tim or indium paste doesn't matter on air/water

if you ramp up the voltage, ivy is simply a monster...hence cooling on ambient isn't good.

clear enough?

[imog]

the tim or indium paste doesn't matter on air/water

if you ramp up the voltage, ivy is simply a monster...hence cooling on ambient isn't good.

clear enough?

Yes, that is clear enough for me to now understand what you mean exactly. Clock is ticking until making fun of you for being wrong commences.

Also FWIW, I think it is possible for Intel to do things that it knows are not the best for cooling, for other reasons - easier to manufacture, good enough, quicker, cheaper etc. It isn't that I think they don't know what they are doing with installing an IHS. I think the temps are not explained by power density, and there are other factors that you (and others) have not accounted for/do not understand which could lead them to using an inferior TIM.

[thegoatman]

I fail to see how ivy can last longer with an average delta-t of +30 degrees C?

[thegoatman]

Yeah seriously.

Intel with its vast resources is questioned. seriously? lol

Several forum members say/question "Intel doesn't know sh*t about installing IHS"

How dare we question a monopolistic corporation whose last competitor in our market niche just flopped, with none to take its place?

[Hondacity]

Yes, that is clear enough for me to now understand what you mean exactly. Clock is ticking until making fun of you for being wrong commences.

Also FWIW, I think it is possible for Intel to do things that it knows are not the best for cooling, for other reasons - easier to manufacture, good enough, quicker, cheaper etc. It isn't that I think they don't know what they are doing with installing an IHS. I think the temps are not explained by power density, and there are other factors that you (and others) have not accounted for/do not understand which could lead them to using an inferior TIM.

read borandi's article. its another take. but basically the same observations.

whoever thought of "power density" is rather mistaken. its mainly controlled leakage versus leakage at higher voltage and clocks. hence there is a ceiling for overclockers on ambient air/water.

as for some that is thermal paste/adhesive as it retains its position once its cured.

[imog]

I see what you are getting at with the leakage comment. I don't agree, but I understand and see why you think that.

I linked Borandi's article in the first paragraph of my article (I have read it).

[Sparky]

If theres a problem, I'm sure Intel will be on top of it by now...especially when it comes to "heat".

Maybe, maybe not. Up through SB they still hadn't figured out how to consistently make a FLAT IHS. My i7 950 is horribly concave to the point that even with a massive cooler it still runs stupidly warm at stock speeds. My 2600k isn't near as bad but still has enough of a dish shape to affect temperatures.

[Hondacity]

Leakage Current

First of all, as chip geometries shrink and clock frequencies rise, the transistor
leakage current increases

Currently, every one percent improvement in processor performance brings a three percent increase in power consumption.
This is because, as transistors shrink and more are packed into smaller space, and as clock frequencies increase, the leakage
current likewise increases, driving up heat and power inefficiency. If transistor density continues to increase at present rates
without improvements in power management, by 2015 microprocessors will consume tens of thousands of watts per
square centimeter.

[zanzabar]

Leakage Current

that would have us with 5-6nm, also isnt it that for every .5x in shrink you gain 4x the transistors in a given area so the wattage goes down but the power consumption pen mm^2 goes up, ending with lower power consumption per given transistor count.

[Hondacity]

leakage current @ stock is controlled.

once you go out of spec(vcc set to max or setting a higher clock speed) then ..leakage is increased. for ivy, her leakage is tremendous lol

[imog]

Holy crap. The document those quotes were pulled from was written in 2005 and you are re-purposing it now to explain these specific heat problems with Ivy Bridge in 2012, while ignoring that IB is the same microarchitecture as SB and we have proof that the TIM is different under the IHS now. It's like the documents prediction came true overnight when IB was released!

Time to retreat to sanity...

[Hondacity]

its related to transistor leakage current. its one of the main concern for cpu design. basically keeping the temperature down.

[RPGWiZaRD]

Maybe it will be popping time, maybe not. All I remember is that popping off IHS on my stupid hot Opteron 165 made the temps go like 14~18C lower.

[Sparky]

Maybe it will be popping time, maybe not. All I remember is that popping off IHS on my stupid hot Opteron 165 made the temps go like 14~18C lower.

You had a crappy IHS mount on yours too huh? I did the same, very nervewracking doing it for the first time ever on my (then) new expensive CPU as an utterly broke college kid.

I drilled a hole in the IHS corner and used it as my keychain for a while

[Dumo]

So what's the problem then? Now peep finally can poured LN2 to full pot like good ol' Phenom and drink 40s waiting for 3D'05 to finish. Lol

Probly Intel should make Ivy better on air for the next revision even if it gonna cb'ed @ -40C

[Hondacity]

word! lol

[Lucky_n00b]

So what's the problem then? Now peep finally can poured LN2 to full pot like good ol' Phenom and drink 40s waiting for 3D'05 to finish. Lol

Probly Intel should make Ivy better on air for the next revision even if it gonna cb'ed @ -40C

Hell No !! I love Ivy the way it is

That said, I'm now a bit curious about how de-lidding the CPU will give advantages for LN2 OCers (aside from cracking the core when putting a pot on that 'defenseless' chip LOL :p)

[Callsign_Vega]

I'd wager properly soldering the IHS on with special equipment is more costly than dabbing a few drops of crappy TIM on there and securing the IHS.

[Hondacity]

Hell No !! I love Ivy the way it is

That said, I'm now a bit curious about how de-lidding the CPU will give advantages for LN2 OCers (aside from cracking the core when putting a pot on that 'defenseless' chip LOL :p)

video please

go go go

[boost]

Is this a retail chip or an ES sample?

[owikh84]

Intel thermal specs does mention about TIM applied on IB
http://www.intel.com/content/www/us/...ket-guide.html


Edit: TIM =! thermal paste only but including solder