Ivy Bridge Temperatures Could Be Linked To TIM Inside Integrated Heatspreader: Report

[CrazyNutz]

Ivy has less die surface area to dissipate heat, then you compound the problem with 3d transistors, the third dimension being on a vertical plane.

[basserdan]

Ivy has less die surface area to dissipate heat, then you compound the problem with 3d transistors, the third dimension being on a vertical plane.

That would seem to make good sense.

I thought I read that this was supposed to relieve the the tightly packed circuits laid out across the individual planes. Removing the "right next together-ness" situation in which the pathways were cumulatively heating each and actually created higher temps. Wouldn't that be funny if this dropped the overall temp but was too inefficient in passing on heat from deep inside. Before: high temps that wicked away easily, now: lower temps that have a harder time leaving the chip = same temps.

[n00b 0f l337]

https://decryptedtech.com/index.php?...ial&Itemid=138

Tested.

Same thing with pre-IHS days and when people popped the top. Difference is negligible. Best thing is still to lap your IHS.

[M.Beier]

https://decryptedtech.com/index.php?...ial&Itemid=138

Tested.

Same thing with pre-IHS days and when people popped the top. Difference is negligible. Best thing is still to lap your IHS.

Grease: Prolimatech PK-1 (10.2/mK)
What was the figure on the solution of the previous one? Almost 7 times higher.

EDIT:
More, not almost..
87w/mK

[Lanek]

https://decryptedtech.com/index.php?...ial&Itemid=138

Tested.

Same thing with pre-IHS days and when people popped the top. Difference is negligible. Best thing is still to lap your IHS.

thats really old school, the last time i have feel the need to lap an IHS or remove it, was .. huum A64 FX period ? for win 20-30mhz ..

[rge]

Intel has already said via third party its thermal (power) density and die attach differences.

Intel in several slide presentations talks about increase power/thermal density with die shrinks (critical dimension decrease). Critical dimension does not equate to die size in sq mm2, power density is not uniformly spread across die. The majority of power in die is consumed over a small area, causing hot spots (where core temp sensors lie), and as the critical dimension decreases the small areas that consume high wattage, get smaller and if consuming same power then much hotter temps. I posted this slide few days ago (and one just like it few years ago). But shrinking CD going from 32 to 22nm, unless you decrease the power, you increase the local thermal density of hot spots. 150W consumed over small enough area = nuclear reactor temps. See slide below.

That being said, solder thermal resistance on one cpu was ~ 0.01C/W (irrelevant other than ratios). Cooling 150 watts, that would be 1.5C gradient across solder interface. There are paste die attaches (requiring baking at 150C to set/cure/reduce air pockets voids) that at best still measure several x higher resistance than solder, cost varies, resistance varies per package, and no one knows what intel is using. But baked on die pastes are better than user tim, I guess we arent using them since curing is at 150C, similar temps to intels solder tim. But if 5x more resistance, then would be 6C temp difference between solder and paste at 150W and less than 3C at stock settings (incorrectly assuming resistance same on ivy vs one measured, and assuming ratio similar). But without a starting point, left guessing, other than clearly will be some significant difference at 150W oced.

As to the individual that removed the IHS and replaced with user tim, would need to reproduce die attach resistance (bondline thickness/contact resistance/bulk thermal conductance) and contact pressure otherwise not any better than guessing. Tim1 interface much more important than tim2, as surface area many times smaller via size difference of die/ihs, and die much less uniform heat/still hot spots vs less so with ihs.

pd.jpg

[paulbagz]

thats really old school, the last time i have feel the need to lap an IHS or remove it, was .. huum A64 FX period ? for win 20-30mhz ..

My QX9650 is lapped

-PB

[Mats]

Not news really, but Techreport explained the heat issue the easy way - just look at the overvolting needed for IB compared to SB at 4.9 GHz: 33.6% vs 11.4%.

I have no doubt that IB will benefit from a newer stepping, although I'm not sure it'll will show up, given that Haswell isn't far away.

[M.Beier]

Not news really, but Techreport explained the heat issue the easy way - just look at the overvolting needed for IB compared to SB at 4.9 GHz: 33.6% vs 11.4%.

I have no doubt that IB will benefit from a newer stepping, although I'm not sure it'll will show up, given that Haswell isn't far away.

A year.

[bamtan2]

needs more vapor chamber, not heat pipe. vapor chambers keep getting better and better, and it is only a matter of time before they are appropriate for this application, if they arent already. high end video card chips put more heat into their vapor chambers than most cpu heatsinks will ever get...

[Sparky]

thats really old school, the last time i have feel the need to lap an IHS or remove it, was .. huum A64 FX period ? for win 20-30mhz ..

I'll give you my i7 950 and then you'll feel the need again

[initialised]

Thinking outside the box for a minute, I bet removing or lapping your the IHS would void Intel's overclocking insurance...

[AFQ]

Intel tells that its due to the heat density which is a result of die shrink:
http://www.maximum-tech.net/intel-ad...-shrink-12410/

[M.Beier]

Intel tells that its due to the heat density which is a result of die shrink:
http://www.maximum-tech.net/intel-ad...-shrink-12410/

Other staff claims that it is because we should rethink cooling, it isnt Intels fault, everyone else whom are redneck suckers.

Anyhow, a realistic combination is DIE shrink, with higher ratio of GPU:CPU, the surface area of CPU has decreased alot...
Intel could solve it by using half layer on the wafer, and double the surface area... But that would cost way too much, and if not entirely redesign the chip, it would hit performance (further distance in DIE)...
Just my thought.

[Manicdan]

Anyhow, a realistic combination is DIE shrink, with higher ratio of GPU:CPU, the surface area of CPU has decreased alot...

pretty much exactly what i said
maybe they should have put 2 cores on either side with L3/gpu in center

[PatRaceTin]

would some IVY model without graphic core release soon like 2550K

[M.Beier]

would some IVY model without graphic core release soon like 2550K

Wont help the OC, and with virtue, we wouldnt want that in generel

[BeepBeep2]

needs more vapor chamber, not heat pipe. vapor chambers keep getting better and better, and it is only a matter of time before they are appropriate for this application, if they arent already. high end video card chips put more heat into their vapor chambers than most cpu heatsinks will ever get...

I thought the same thing a few days ago. What if we had a vapor chamber IHS?

Or better yet, IHS-less CPU and stock cooler with vapor chamber base with aluminum fins soldered?

[Levish]

I wonder if jet impingement water blocks will be making a comeback

[mAJORD]

I wonder if jet impingement water blocks will be making a comeback

I've been wondering the same thing.. At least till multithreaded performance finally becomes a client priority and big dies make a return on the desktop

Sent from my GT-I9100 using Tapatalk 2

[Mats]

http://vr-zone.com/articles/ivy-brid...ase/15844.html

They should have done the same with a 2700K as a comparison.

[hokiealumnus]

The thanks button appears to be missing, but thanks Mats.

They couldn't do the same with a 2700K though; SNB is soldered.

[Mats]

Yeah but you know, heat it up and remove it.

a stable 5GHz overclock on air at 1.55V

[BeepBeep2]

Why is it that some people seem to see a huge difference in temps after delidding and others see almost none? ...but changing thermal paste nets 10-15c+?

O_o

[osiris999]

I have a 3770k coming next week. Really tempted to pop the top on her now. Gonna be water cooled so might even be able to go above 5ghz. Would tim like as5 and mx-4 work?